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cynse7012 8 cypress semiconductor corporation ? 3901 north first street san jose , ca 95134 408-943-2600 document #: 38-02040 rev. *e revised june 23, 2003 cynse70128 network search engine
cynse7012 8 document #: 38-02040 rev. *e page 2 of 137 contents 1.0 overview .................................................................................................................. .................... 9 2.0 features .................................................................................................................. .................... 9 3.0 functional description .................................................................................................... ... 10 3.1 command bus and dq bus .................................................................................................... .. 10 3.2 database entry (data array and mask array) .......................................................................... 10 3.3 arbitration logic ......................................................................................................... ............... 11 3.4 pipeline and sram control ................................................................................................. ..... 11 3.5 full logic ................................................................................................................ ................... 11 4.0 signal descriptions ....................................................................................................... ....... 11 5.0 clocks..................................................................................................................... ..................... 13 6.0 phase-lock loop usage ..................................................................................................... .. 15 7.0 registers ................................................................................................................. .................. 15 7.1 comparand registers ....................................................................................................... ........ 15 7.2 mask registers ............................................................................................................ ............. 16 7.3 search successful registers (ssr[0:7]) .................................................................................. 16 7.4 command register .......................................................................................................... ......... 17 7.5 information register ...................................................................................................... ............ 18 7.6 read burst address register ............................................................................................... .... 18 7.7 write burst address register description ................................................................................. 1 9 7.8 nfa register .............................................................................................................. .............. 19 8.0 nse architecture and operation overview ............................................................... 19 9.0 data and mask addressing ................................................................................................ 21 10.0 commands ................................................................................................................. ............... 21 10.1 command codes ............................................................................................................ ........21 10.2 commands and command parameters ................................................................................. 22 10.3 read command ............................................................................................................. ......... 22 10.4 write command ............................................................................................................ ..........25 10.5 parallel write ........................................................................................................... ................ 27 10.6 search command ........................................................................................................... ........ 27 10.6.1 72-bit search on tables configured as 72 using a single cynse70128 device ...................... 27 10.6.2 72-bit search on tables configured as 72 using up to eight cynse70128 devices ................30 10.6.3 72-bit search on tables configured as x72 using up to 31 cynse70128 devices .................... 36 10.6.4 144-bit search on tables configured as x144 using a single cynse70128 device .................. 51 10.6.5 144-bit search on tables configured as x144 using up to eight cynse70128 devices ............ 53 10.6.6 144-bit search on tables configured as x144 using up to 31 cynse70128 devices ................59 10.6.7 288-bit search on tables configured as x288 using a single cynse70128 device .................. 74 10.6.8 288-bit search on tables configured as x288 using up to eight cynse70128 devices ............ 76 10.6.9 288-bit search on tables configured as x288 using up to 31 cynse70128 devices ................82 10.6.10 mixed-size searches on tables configured with different widths using a cynse70128 with cfg_l low ..................................................................................................................... ....................... 97 10.6.11 mixed-size searches on tables configured to different widths using a cynse70128 with cfg_l high .......................................................................................................................... .............................. 98 10.7 lram and ldev description ................................................................................................ .. 98 10.8 learn command ............................................................................................................ ......... 98
cynse7012 8 document #: 38-02040 rev. *e page 3 of 137 table of contents (continued) 11.0 depth-cascading .......................................................................................................... ....... 102 11.1 depth-cascading up to eight devices (one block) .............................................................. 102 11.2 depth-cascading up to 31 devices (four blocks) ................................................................ 103 11.3 depth-cascading for a full signal .....................................................................................104 12.0 sram addressing .......................................................................................................... ...... 105 12.1 generating an sram bus address .....................................................................................106 12.2 sram pio access .......................................................................................................... ...... 106 12.3 sram read with a table of one device .............................................................................. 106 12.4 sram read with a table of up to eight devices .................................................................. 107 12.5 sram read with a table of up to 31 devices ...................................................................... 110 12.6 sram write with a table of one device .............................................................................. 113 12.7 sram write with a table of up to eight devices .................................................................. 114 12.8 sram write with table(s) of up to 31 devices ..................................................................... 117 13.0 power .................................................................................................................... .................. 121 13.1 power-up sequence ........................................................................................................ ..... 121 13.2 power consumption ........................................................................................................ ...... 121 14.0 application .............................................................................................................. ............. 123 15.0 jtag (1149.1) testing .................................................................................................... ....... 123 16.0 electrical specifications ..............................................................................................12 4 17.0 ac timing waveforms ...................................................................................................... .. 125 17.1 special note for multi_hit function on the cynse70128 ................................................ 129 18.0 pinout description ....................................................................................................... ...... 130 19.0 ordering information ..................................................................................................... . 135 20.0 package diagram .......................................................................................................... ...... 136
cynse7012 8 document #: 38-02040 rev. *e page 4 of 137 list of figures figure 5-1. cynse70128 clocks (clk2x and phs_l) ........................................................................ 13 figure 5-2. cynse70128 clocks (clk1x) .......................................................................................... .13 figure 5-3. cynse70128 clocks for all timing diagrams.................................................................... 14 figure 7-1. comparand-register selection during search and learn instructions ............................... 15 figure 7-2. addressing the global mask register array ....................................................................... 16 figure 8-1. cynse70128 database width configuration ..................................................................... 19 figure 8-2. multiwidth database configurations example ..................................................................... 21 figure 9-1. addressing the cynse70128 data and mask arrays ........................................................ 21 figure 10-1. single-location read cycle timing ................................................................................. .23 figure 10-2. burst read of the data and mask arrays (blen = 4) ....................................................... 24 figure 10-3. single write cycle timing ......................................................................................... ........ 25 figure 10-4. burst write of the data and mask arrays (blen = 4) ....................................................... 26 figure 10-5. timing diagram for 72-bit search in x72 table (one device)........................................... 28 figure 10-6. hardware diagram for a table with one device ............................................................... 28 figure 10-7. x72 table with one device ......................................................................................... ...... 29 figure 10-8. hardware diagram for a table with eight devices............................................................ 31 figure 10-9. timing diagram for 72-bit search device number 0......................................................... 32 figure 10-10. timing diagram for 72-bit search device number 1....................................................... 33 figure 10-11. timing diagram for 72-bit search device number 7 (last device) ................................ 34 figure 10-12. x72 table with eight devices ..................................................................................... ..... 35 figure 10-13. hardware diagram for a table with 31 devices.............................................................. 37 figure 10-14. hardware diagram for a block of up to eight devices .................................................... 38 figure 10-15. timing diagram for each device in block number 0 (miss on each device) ................. 39 figure 10-16. timing diagram for each device above the winning device in block number 1 ........... 40 figure 10-17. timing diagram for globally winning device in block number 1 ................................... 41 figure 10-18. timing diagram for devices below the winning device in block number 1 ................... 42 figure 10-19. timing diagram for devices above the wi nning device in block number 2 .................. 43 figure 10-20. timing diagram for globally winning device in block number 2 ................................... 44 figure 10-21. timing diagram for devices below the winning device in block number 2 ................... 45 figure 10-22. timing diagram for devices above the wi nning device in block number 3 .................. 46 figure 10-23. timing diagram for globally winning device in block number 3 ................................... 47 figure 10-24. timing diagram for devices below the winning device in block number 3 (except the last device [device 30])........................................................................................... .......... 48 figure 10-25. timing diagram for device number 6 in block number 3 (device 30 in depth-cascaded table)............................................................................................ ....... 49 figure 10-26. x72 table with 31 devices ........................................................................................ ...... 50 figure 10-27. timing diagram for 144-bit search (one device) ........................................................... 51 figure 10-28. hardware diagram for a table with one device ............................................................ 51 figure 10-29. x144 table with one device ....................................................................................... .... 52 figure 10-30. hardware diagram for a table with eight devices.......................................................... 54 figure 10-31. timing diagram for 144-bit search device number 0..................................................... 55 figure 10-32. timing diagram for 144-bit search device number 1..................................................... 56 figure 10-33. timing diagram for 144-bit search device number 7 (last device) .............................. 57 figure 10-34. x144 table with eight devices .................................................................................... .... 58 figure 10-35. hardware diagram for a table with 31 devices.............................................................. 60 figure 10-36. hardware diagram for a block of up to eight devices .................................................... 61 figure 10-37. timing diagram for each device in block number 0 (miss on each device) ................. 62 figure 10-38. timing diagram for each device above the winning device in block number 1 ........... 63 figure 10-39. timing diagram for globally winning device in block number 1 ................................... 64
cynse7012 8 document #: 38-02040 rev. *e page 5 of 137 list of figures (continued) figure 10-40. timing diagram for devices below the winning device in block number 1 ................... 65 figure 10-41. timing diagram for devices above the wi nning device in block number 2 .................. 66 figure 10-42. timing diagram for globally winning device in block number 2 ................................... 67 figure 10-43. timing diagram for devices below the winning device in block number 2 ................... 68 figure 10-44. timing diagram for devices above the wi nning device in block number 3 .................. 69 figure 10-45. timing diagram for globally winning device in block number 3 ................................... 70 figure 10-46. timing diagram for devices below the winning device in block number 3 except device 30 (the last device)............................................................................................. .......... 71 figure 10-47. timing diagram for device number 6 in block number 3 (device 30 in depth-cascaded table)....................................................................................................... .............. 72 figure 10-48. x144 table with 31 devices ....................................................................................... ..... 73 figure 10-49. timing diagram for 288-bit search (one device) ........................................................... 74 figure 10-50. hardware diagram for a table with one device............................................................. 75 figure 10-51. x288 table with one device ....................................................................................... .... 75 figure 10-52. hardware diagram for a table with eight devices.......................................................... 77 figure 10-53. timing diagram for 288-bit search device number 0..................................................... 78 figure 10-54. timing diagram for 288-bit search device number 1..................................................... 79 figure 10-55. timing diagram for 288-bit search device number 7 (last device) .............................. 80 figure 10-56. x288 table with eight devices .................................................................................... .... 81 figure 10-57. hardware diagram for a table with 31 devices.............................................................. 83 figure 10-58. hardware diagram for a block of up to eight devices .................................................... 84 figure 10-59. timing diagram for each device in block number 0 (miss on each device) ................. 85 figure 10-60. timing diagram for each device above the winning device in block number 1 ........... 86 figure 10-61. timing diagram for globally winning device in block number 1 ................................... 87 figure 10-62. timing diagram for devices below the winning device in block number 1 ................... 88 figure 10-63. timing diagram for devices above the wi nning device in block number 2 .................. 89 figure 10-64. timing diagram for globally winning device in block number 2 ................................... 90 figure 10-65. timing diagram for devices below the winning device in block number 2 ................... 91 figure 10-66. timing diagram for devices above the wi nning device in block number 3 .................. 92 figure 10-67. timing diagram for globally winning device in block number 3 ................................... 93 figure 10-68. timing diagram for devices below the winning device in block number 3 except device 30 (the last device)............................................................................................. .......... 94 figure 10-69. timing diagram of the last device in block number 3 (device 30 in the table)............ 95 figure 10-70. x288 table with 31 devices ....................................................................................... ..... 96 figure 10-71. timing diagram for mixed search (one device)............................................................. 97 figure 10-72. multiwidth configurations example ................................................................................ .98 figure 10-73. timing diagram of learn (tlsz = 00)............................................................................. 9 9 figure 10-74. timing diagram of learn (except on the last device [tlsz = 01]).............................. 100 figure 10-75. timing diagram of learn on device number 7 (tlsz = 01)......................................... 101 figure 11-1. depth-cascading to form a single block ....................................................................... 103 figure 11-2. depth-cascading four blocks....................................................................................... .. 104 figure 11-3. full generation in a cascaded table........................................................................... 105 figure 12-1. sram read access (tlsz = 00, hlat = 000, lram = 1, ldev = 1)........................... 107 figure 12-2. table of a block of eight devices................................................................................. ... 108 figure 12-3. sram read through device number 0 in a block of eight devices.............................. 109 figure 12-4. sram read timing for device number 7 in a block of eight devices ........................... 110 figure 12-5. table of 31 devices made of four blocks....................................................................... 111 figure 12-6. sram read through device number 0 in a block of 31 devices (device number 0 timing)....................................................................................................... ............ 112
cynse7012 8 document #: 38-02040 rev. *e page 6 of 137 list of figures (continued) figure 12-7. sram read through device number 0 in a block of 31 devices (device number 30 timing) ...................................................................................................... ........... 113 figure 12-8. sram write access (tlsz = 00, hlat = 000, lram = 1, ldev = 1) ........................... 114 figure 12-9. table of a block of eight devices................................................................................. ... 115 figure 12-10. sram write through device number 0 in a block of eight devices............................ 116 figure 12-11. sram write timing for device number 7 in a block of eight devices ......................... 117 figure 12-12. table of 31 devices (four blocks) ................................................................................ 118 figure 12-13. sram write through device number 0 in a bank of 31 devices (device 0 timing) ... 119 figure 12-14. sram write through device number 0 in a bank of 31 cynse70128 devices (device number 30 timing) ...................................................................................................... ........... 120 figure 13-1. power-up sequence (clk2x)......................................................................................... .121 figure 13-2. power consumption of cynse70128............................................................................. 122 figure 14-1. sample switch/router using the cynse70128 device ................................................. 123 figure 17-1. input wave form for cynse70128 ................................................................................ 127 figure 17-2. output load for cynse70128 ........................................................................................ 127 figure 17-3. i/o output load equivalent for cynse70128 ................................................................ 127 figure 17-4. ac timing waveforms with clk2x................................................................................. 128 figure 17-5. ac timing waveforms with clk1x................................................................................. 129 figure 18-1. pinout diagram.................................................................................................... ............ 130 figure 20-1. 388-lead ball grid array (35 x 35 x 2.33 mm) bg388..................................................... 136
cynse7012 8 document #: 38-02040 rev. *e page 7 of 137 list of tables table 4-1. cynse70128 signal description ...................................................................................... .. 11 table 7-1. register overview .................................................................................................. ............. 15 table 7-2. search successful register description ............................................................................. 16 table 7-3. command register description ....................................................................................... .... 17 table 7-4. information register description ................................................................................... ...... 18 table 7-5. read burst register description .................................................................................... ..... 18 table 7-6. write burst register description ................................................................................... ...... 19 table 7-7. nfa register ....................................................................................................... ................ 19 table 8-1. bit position match ................................................................................................. ............... 20 table 10-1. command codes ..................................................................................................... .......... 22 table 10-2. command parameters ................................................................................................ ...... 22 table 10-3. read command parameters ........................................................................................... .. 23 table 10-4. read address format for data array, mask array, or sram ........................................... 23 table 10-5. read address format for internal registers ..................................................................... 24 table 10-6. read address format for data and mask arrays .............................................................. 25 table 10-7. write address format for data array, mask array or sram (single write) ...................... 26 table 10-8. write address format for internal registers ..................................................................... 26 table 10-9. write address format for data and mask array (burst write) .......................................... 27 table 10-10. the latency of search from instruction to sram access cycle ..................................... 29 table 10-11. shift of ssf and ssv from sadr ................................................................................. 29 table 10-12. hit/miss assumption .............................................................................................. .......... 30 table 10-13. the latency of search from instruction to sram access cycle ..................................... 35 table 10-14. shift of ssf and ssv from sadr ................................................................................. 35 table 10-15. hit/miss assumption .............................................................................................. .......... 36 table 10-16. the latency of search from instruction to sram access cycle ..................................... 50 table 10-17. shift of ssf and ssv from sadr ................................................................................... 50 table 10-18. the latency of search from instruction to sram access cycle ..................................... 52 table 10-19. shift of ssf and ssv from sadr ................................................................................. 52 table 10-20. hit/miss assumption .............................................................................................. .......... 53 table 10-21. search latency from instruction to sram access cycle ................................................ 58 table 10-22. shift of ssf and ssv from sadr ................................................................................. 58 table 10-23. hit/miss assumption .............................................................................................. .......... 59 table 10-24. the latency of search from instruction to sram access cycle ..................................... 73 table 10-25. shift of ssf and ssv from sadr ................................................................................. 73 table 10-26. the latency of search from cycles c and d to sram access cycle ............................ 76 table 10-27. shift of ssf and ssv from sadr ................................................................................. 76 table 10-28. hit/miss assumption .............................................................................................. .......... 76 table 10-29. the latency of search from cycles c and d to sram access cycle ............................ 81 table 10-30. shift of ssf and ssv from sadr ................................................................................... 81 table 10-31. hit/miss assumption .............................................................................................. .......... 82 table 10-32. the latency of search from cycles c and d to sram access cycle ............................ 96 table 10-33. shift of ssf and ssv from sadr ................................................................................... 96 table 10-34. searches with cfg_l set high ..................................................................................... .. 98 table 10-35. latency of sram write cycle from second cycle of learn instruction ........................ 101 table 12-1. sram address ...................................................................................................... ..........106 table 15-1. supported operations .............................................................................................. ....... 123 table 15-2. tap device id register ............................................................................................ ....... 124 table 16-1. dc electrical characteristics for cynse70128 .............................................................. 124 table 16-2. operating conditions for cynse70128 ..........................................................................125
cynse7012 8 document #: 38-02040 rev. *e page 8 of 137 list of tables (continued) table 17-1. ac timing parameters with clk2x ................................................................................ 125 table 17-2. ac timing parameters with clk1x ................................................................................ 126 table 17-3. 2.5v ac table for test condition of cynse70128 ........................................................ 126 table 18-1. pinout descriptions for pinout diagram ........................................................................... 1 31 table 19-1. ordering information .............................................................................................. ..........135
cynse7012 8 document #: 38-02040 rev. *e page 9 of 137 1.0 overview cypress semiconductor corporation?s (cypress?s) cynse70128 network search engine (nse) incorporates patent-pending associative processing technology? (apt) and is designed to be a high-performance, pipelined, synchronous, 64k-entry nse. the cynse70128 database entry size can be 72 bits, 144 bits, or 288 bits. in the 72-bit entry mode, the size of the database is 64k entries. in the 144-bit mode, the size of the database is 32k entries, and in the 288-bit mode, the size of the database is 16k entries. the cynse70128 device is configurable to support multiple databases with different entry sizes. the 36-bit entry table can be implemented using the global mask registers (gmrs) building-database size of 128k entries with a single device. the nse can sustain 100 million transactions per second when the database is programmed or configured as 72 or 144 bits. when the database is programmed to have an entry size of 36 or 288 bits, the nse will perform at 50 million transactions per second. the cynse70128 can be used to accelerate network protocols such as longest-prefix match (cidr), arp, mpls, and other layer 2, 3, and 4 protocols. this high-speed, high-capacity nse can be deployed in a variety of networking and communications applications. the perfor- mance and features of the cynse70128 make it attractive in applications such as enterprise lan switches and routers and broadband switching and/or routing equipment supporting multiple data rates at oc?48 and beyond. the nse is designed to be scalable in order to support network database sizes to 3968k entries specifically for environments that require large network policy databases. the block diagram for the cynse70128 device is shown on page 10. 2.0 features ? 128k 36-bit entries in a single device 64k entries in 72-bit mode, 32k entries in 144-bit mode, 16k entries in 288-bit mode 100 million transactions per second in 72- and 144-bit configurations 50 million transactions in 36- and 288-bit configurations searches any subfield in a single cycle synchronous pipelined operation up to 31 nses can be cascaded when cascaded, the database entries can range up to 3,968k 36-bit entries multiple width tables in a single database bank glueless interface to industry-standard srams and/or ssrams simple hardware instruction interface ieee 1149.1 test access port 1.5v core voltage supply up to 83 million searches per second (msps)/1.65v core voltage supply for search rates greater than 83 msps 2.5/3.3v i/o voltage supply 388-pin bga package .
cynse7012 8 document #: 38-02040 rev. *e page 10 of 137 3.0 functional description the following subsections contain command and dq bus (command and databus), database entry, arbitration logic, pipeline and sram control, and full logic descriptions. 3.1 command bus and dq bus cmd[10:0] carries the command and its associated parameter. dq[71:0] is used for data transfer to and from the database entries , which comprise a data and a mask field that are organized as data and mask arrays. the dq bus carries the search data (of the data and mask arrays and internal registers) during the search command as well as the address and data during read and/or write operations. the dq bus can also carry the address information for the flow-through accesses to the external srams and/or ssrams. 3.2 database entry (data array and mask array) each database entry comprises a data and a mask field. the resultant value of the entry is ?1,? ?0,? or ?x (don?t care),? depen ding on the value in the data and mask bits. the on-chip priority encoder selects the first matching entry in the database that is n earest to location 0. compare/pio data address decode match logic compare/pio data dq[71:0] cmdv cmd[10:0] lhi[6:0] command and pio access priority encode cmd arbitration logic lho[1:0] pipeline and sram control sadr[23:0] oe_l bho[2:0] ssf we_l ce_l id[4:0] bhi[2:0] ssv ack tap tap controller ale_l fulo[1:0] fuli[6:0] eot full logic full rst_l phs_l decode comparand register pairs [15:0] global mask register pairs [15:0] information and command register burst read register burst write register next-free address register search successful index registers [7:0] clk1x/clk2x [all registers are 72 bits wide.] configurable as 64k 72 32k 144 16k 288 mask array configurable as 64k 72 32k 144 16k 288 data array clk_mode block diagram
cynse7012 8 document #: 38-02040 rev. *e page 11 of 137 3.3 arbitration logic when multiple nses are cascaded to create large databases, the data being searched is presented to all nses simultaneously in the cascaded system. if multiple matches occur within the cascaded devices, arbitration logic on the nses will enable the winning device (with a matching entry that is closest to address 0 of the cascaded database) to drive the sram bus. 3.4 pipeline and sram control pipeline latency is added to give enough time to a cascaded system?s arbitration logic to determine the device that will drive the index of the matching entry on the sram bus. pipeline logic adds latency to both the sram access cycles and the ssf and ssv signals to align them to the host asic receiving the associated data. 3.5 full logic bit[0] in each of the 72-bit entries has a special purpose for the learn command (0 = empty, 1 = full). when all the data entri es have bit[0] = 1, the database asserts the full flag, indicating that all the nses in the depth-cascaded array are full. 4.0 signal descriptions table 4-1 lists and describes all cynse70128 signals. table 4-1. cynse70128 signal description pin name pin type [1] pin description clocks and reset clk_mode i clock mode: this signal allows the selection of clock (clk [2] ) input to the clk1x/clk2x pin. if the clk_mode pin is low, clk2x must be supplied on that pin. phs_l must also be supplied. if the clk_mode pin is high, clk1x must be supplied on the clk2x/clk1x pin, and the phs_l signal is not required. when the clk_mode is high, phs_l is unused and should be externally grounded. clk2x/clk1x i master clock: depending on the clk_mode pin, either the clk2x or the clk1x must be supplied. cynse70128 samples control and data signals on both the edges of clk1x (if clk1x is supplied). cynse70128 samples all the data and control pins on the positive edge of clk2x if the clk2x and phs_l signals are supplied. all signals are driven out of the device on the rising edge of clk1x if clk1x is supplied, and are driven on the rising edge of clk2x (when phs_l is low) if clk2x is supplied. phs_l i phase: this signal runs at half the frequency of clk2x and generates an internal clock from clk2x. see ?clocks? on page 13. rst_l i reset: driving rst_l low initializes the device to a known state. cfg_l i configuration: when cfg_l is low, cynse70128 will operate in backward compatibility mode with cynse70032 and cynse70064. when cfg_l is low, the cmd[10:9] should be externally grounded. with cfg_l low, the device will behave identically with cynse70032 and cynse70064, and the new feature added to cynse70128 will be disabled. when cfg_l is high, the additional command cmd[10:9] can be used and the following additional features will be supported: 1. 16 pair of global masks are supported instead of eight; 2. parallel write to the data and mask arrays is supported (see ?parallel write? on page 27); and 3. configuring tables of up to three different widths does not require table identification bits in the data array, thus saving two bits from each 72-bit entry. command and dq bus cmd[10:0] i command bus: [1:0] specifies the command and [10:2] contains the command parameters. the descrip- tions of individual commands explains the details of the parameters. the encoding of commands based on the [1:0] field are: 00: pio read 01: pio write 10: search 11: learn. cmdv i command valid: this signal qualifies the cmd bus: 0: no command 1: command. notes: 1. i = input only, i/o = input or output, o = output only, t = three-state output. 2. ?clk? is an internal clock signal.
cynse7012 8 document #: 38-02040 rev. *e page 12 of 137 dq[71:0] i/o address/data bus: this signal carries the read and write address and data during register, data, and mask array operations. it carries the compare data during search operations. it also carries the sram address during sram pio accesses. ack [5] t read acknowledge: this signal indicates that valid data is available on the dq bus during register, data, and mask array read operations, or that the data is available on the sram data bus during sram read operations. eot [5] t end of transfer: this signal indicates the end of burst transfer to the data or mask array during read or write burst operations. ssf t search successful flag: when asserted, this signal indicates that the device is the global winner in a search operation. ssv t search successful flag valid: when asserted, this signal qualifies the ssf signal. multi_hit o multiple hit flag: when asserted, this signal indicates that there is more than one location having a match on this device. high_speed i high speed: when this signal is high, the device will run up to 100 mhz and perform 100 msps. however, in this mode, a tlsz value of 00 is not supported when only one device is used. the valid tlsz values are shown in command register description ( table 7-3 ). when the signal is low, the device will run up to 83 mhz and perform 83 msps. sram interface sadr[23:0] t sram address: this bus contains address lines to access off-chip srams that contain associative data. see table 12-1 for the details of the generated sram address. in a database of multiple cynse70128s, each corresponding bit of sadr from all cascaded devices must be connected. ce_l t sram chip enable: this is the chip-enable control for external srams. in a database of multiple cynse70128s, ce_l of all cascaded devices must be connected. this signal is then driven by only one of the devices. we_l t sram write enable: this is the write-enable control for external srams. in a database of multiple cynse70128s, we_l of all cascaded devices must be connected together. this signal is then driven by only one of the devices. oe_l t sram output enable: this is the output-enable control for external srams. only the last device drives this signal (with the lram bit set). ale_l t address latch enable: when this signal is low, the addresses are valid on the sram address bus. in a database of multiple cynse70128s, the ale_l of all cascaded devices must be connected. this signal is then driven by only one of the devices. cascade interface lhi[6:0] i local hit in: these pins depth-cascade the device to form a larger table. one signal of this bus is connected to the lho[1] or lho[0] of each of the upstream devices in a block. all unused lhi pins are connected to a logic 0. (for more information, see ?depth-cascading? on page 102.) lho[1:0] o local hit out: lho[1] and lho[0] are the same logical signal. either the lho[1] or the lho[0] is connected to one input of the lhi bus of up to four downstream devices in a block of up to eight. (for more information see ?depth-cascading? on page 102.) bhi[2:0] i block hit in: inputs from the previous block bho[2:0] are tied to bhi[2:0] of the current device. in a four- block system, the last block can contain only seven devices because the identification code 11111 is used for broadcast access. bho[2:0] o block hit out: these outputs from the last device in a block are connected to the bhi[2:0] inputs of the devices in the downstream blocks. fuli[6:0] i full in: each signal in this bus is connected to fulo[0] or fulo[1] of an upstream device to generate the full flag for the depth-cascaded block. notes: 3. in the previous versions of this specification, this signal was called clk_out. 4. in previous versions of this specification, this signal was called pll_bypass. 5. ack and eot require a weak external pull-down such as 47 k ? or 100 k ? . table 4-1. cynse70128 signal description (continued) pin name pin type [1] pin description
cynse7012 8 document #: 38-02040 rev. *e page 13 of 137 5.0 clocks [6] if the clk_mode pin is low, cynse70128 receives the clk2x and phs_l signals. it uses the phs_l signal to divide clk2x and generate a clk, as shown in figure 5-1 . the cynse70128 uses clk2x and clk for internal operations. if the clk_mode pin is high, cynse70128 receives the clk1x only. cynse70128 uses an internal pll to double the frequency of clk1x and then divides that clock by two to generate a clk for internal operations, as shown in figure 5-2 . [7] notes: 6. any reference to ?clk? cycles means one clk cycle. 7. for the purpose of showing timing diagrams, all such diagrams in this document will be shown in clk2x mode. for a timing diag ram in clk1x mode, the following substitution can be made (see figure 5-3 ). fulo[1:0] o full out: fulo[1] and fulo[0] are the same logical signal. one of these two signals must be connected to the fuli of up to four downstream devices in a depth-cascaded table. bit [0] in the data array indicates whether the entry is full (1) or empty (0).this signal is asserted if all bits in the data array are ones. (refer to ?depth-cascading? on page 102 for information on how to generate the full flag.) full o full flag: when asserted, this signal indicates that the table of multiple depth-cascaded devices is full. device identification id[4:0] i device identification: the binary-encoded device identification for a depth-cascaded system starts at 00000 and goes up to 11110. 11111 is reserved for a special broadcast address that selects all cascaded nses in the system. on a broadcast read-only, the device with the ldev bit set to 1 responds. supplies v dd n/a chip core supply: 1.5v. (1.65v for search rates greater than 83 msps.) v ddq n/a chip i/o supply: 2.5v or 3.3v (cynse70128-xxx) test access port tdi i test access port?s test data in. tck i test access port?s test clock. tdo t test access port?s test data out. tms i test access port?s test mode select. trst_l i test access port?s reset. table 4-1. cynse70128 signal description (continued) pin name pin type [1] pin description clk2x phs_l clk figure 5-1. cynse70128 clocks (clk2x and phs_l) clk1x clk figure 5-2. cynse70128 clocks (clk1x)
cynse7012 8 document #: 38-02040 rev. *e page 14 of 137 clk2x phs_l clk1x use for clk2x mode use for clk1x mode figure 5-3. cynse70128 clocks for all timing diagrams
cynse7012 8 document #: 38-02040 rev. *e page 15 of 137 6.0 phase-lock loop usage when the device first powers up, it takes 0.5 ms to lock the internal phase-lock loop (pll). during this locking of the pll, in addition to 32 extra clk1x cycles in clk1x mode and 64 extra cycles in clk2x mode, the rst_l must be held low for proper initialization of the device. set-up and hold requirements will change in clk1x mode if the duty cycle of the clk1x is varied. all signals into the device in clk1x mode are sampled by a clock that is generated by multiplying clk1x by two. since pll has a locking range, the device will only work between the range of frequencies specified in the timing specification section. 7.0 registers all registers in the cynse70128 are 72 bits wide. the cynse70128 contains 16 pairs of comparand storage registers, 16 pairs of global mask registers (gmrs), eight search successful index registers and one each of command, information, burst read, burst write, and next-free address registers. table 7-1 provides an overview of all the cynse70128 registers. the registers are ordered in ascending address order. each register group is then described in the following subsections. 7.1 comparand registers the device contains 32 72-bit comparand registers (16 pairs) dynamically selected in every search operation to store the comparand presented on the dq bus. the learn command will later use these registers when executed. the cynse70128 stores the search command?s cycle a comparand in the even-num bered register and the cycle b comparand in the odd-numbered register, as shown in figure 7-1 . table 7-1. register overview address abbreviation type name 0?31 comp0?31 r 16 pairs of comparand registers that store comparands from the dq bus for learning later. 32?47 96?111 masks rw 16 global mask register pairs. 48?55 ssr0?7 r eight search successful index registers. 56 command rw command register. 57 info r information register. 58 rburreg rw burst read register. 59 wburreg rw burst write register. 60 nfa r next-free address register. 61?63 ? ? reserved. 143 0 72 72 1 0 3 2 5 4 7 6 30 31 index 0 15 1 address figure 7-1. comparand-register selecti on during search and learn instructions
cynse7012 8 document #: 38-02040 rev. *e page 16 of 137 7.2 mask registers the device contains 32 72-bit global mask registers (16 pairs) dynamically selected in every search operation to select the sea rch subfield. the addressing of these registers is explained in figure 7-2 . the four-bit gmr index supplied on the command (cmd) bus can apply 16 pairs of global masks during the search and write operations, as shown below. note . in 72-bit search and write operations, the host asic must program both the even and odd mask registers with the same values. each mask bit in the gmrs is used during search and write operations. in search operations, setting the mask bit to 1 enables compares; setting the mask bit to 0 disables compares (forced match) at the corresponding bit position. in write operations to the data or mask array, setting the mask bit to 1 enables writes; setting the mask bit to 0 disables writes at the correspondin g bit position. 7.3 search successful registers (ssr[0:7]) the device contains eight search successful registers (ssrs) to hold the index of the location where a successful search occurred. the format of each register is described in table 7-2 . the search command specifies which ssr stores the index of a specific search command in cycle b of the search instruction. subsequently, the host asic can use this register to access tha t data array, mask array, or external sram using the index as part of the indirect access address (see table 10-4 and table 7-2 ). the device with a valid bit set performs a read or write operation. all other devices suppress the operation. table 7-2. search successful register description field range initial value description index [15:0] x index . this is the address of the 72-bit entry where a successful search occurs. the device updates this field only when the search is successful. if a hit occurs in a 144-bit entry-size quadrant, the lsb is 0. if a hit occurs in a 288-bit entry-size quadrant, the two lsbs are 00. this index updates if the device is either a local or global winner in a search operation. ? [30:16] 0 reserved . valid [31] 0 valid . during search operation in a depth-cascaded configuration, the device that is a global winner in a match sets this bit to 1. this bit updates only when the device is a global winner in a search operation. ? [71:32] 0 reserved . 001 123 245 367 489 51011 61213 71415 81617 91819 10 20 21 11 22 23 12 24 25 13 26 27 14 28 29 15 30 31 index 143 72 72 search and write command global mask selection 0 figure 7-2. addressing the global mask register array
cynse7012 8 document #: 38-02040 rev. *e page 17 of 137 7.4 command register table 7-3 describes the command register fields. table 7-3. command register description field range initial value description srst [0] 0 software reset . if 1, this bit resets the device with the same effect as a hardware reset. internally, it generates a reset pulse lasting for eight clk cycles. this bit automatically resets to 0 after the reset has completed. deve [1] 0 device enable . if 0, it keeps the sram bus (sadr, we_l, ce_l, oe_l, and ale_l), ssf, and ssv signals in three-state condition and forces the cascade interface output signals lho[1:0] and bho[2:0] to 0. it also keeps the dq bus in input mode. the purpose of this bit is to make sure that there are no bus conten- tions when the devices power up in the system. tlsz [3:2] 01 table size . the host asic must program this field to configure the chips into a table of a certain size. this field affects the pipeline latency of the search and learn operations as well as the read and write accesses to the sram (sadr[23:0], ce_l, oe_l, we_l, ale_l, ssv, ssf, and ack). once programmed, the search latency stays constant. latency in number of clk cycles with high_speed low: 00: 1 device 4 01: up to 8 devices 5 10: up to 31 devices 6 11: reserved. latency number clk cycles with high_speed high: 00: not supported 01: 1 device 5 10: 2?31 devices 6 11: reserved. hlat [6:4] 000 latency of hit signals . this field further adds latency to the ssf and ssv signals during search, and ack signal during sram read access by the following number of clk cycles. 000: 0 100: 4 001: 1 101: 5 010: 2 110: 6 011: 3 111: 7 ldev [7] 0 last device in the cascade . when set, this is the last device in the depth- cascaded table and is the default driver for the ssf and ssv signals. in the event of a search failure, the device with this bit set drives the hit signals as follows: ssf = 0, ssv = 1. during nonsearch cycles, the device with this bit set drives the signals as follows: ssf = 0, ssv = 0. lram [8] 0 last device on the sram bus . when set, this device is the last device on the sram bus in the depth-cascaded table and is the default driver for the sadr, ce_l, we_l, and ale_l signals. in cycles where no cynse70128 device in a depth cascaded table drives these signals, this devices drives the signals as follows: sadr = 24?hffffff, ce_l = 1, we_l = 1, and ale_l = 1. oe_l is always driven by the device for which this bit is set.
cynse7012 8 document #: 38-02040 rev. *e page 18 of 137 7.5 information register table 7-4 describes the information register fields. 7.6 read burst address register table 7-5 shows the read burst address register (rburreg) fields which must be programmed before a burst read. cfg [24:9] 0000000000000000 database configuration . the device is divided internally into eight partitions of 8k 72, each of which can be configured as 8k 72, 4k 144, or 2k 288, as follows. 00: 8k 72 01: 4k 144 10: 2k 288 11: low power, partition not used for search. bits [10:9] apply to configuring the first partition in the address space. bits [12:11] apply to configuring the second partition in the address space. bits [14:13] apply to configuring the third partition in the address space. bits [16:15] apply to configuring the fourth partition in the address space. bits [18:17] apply to configuring the fifth partition in the address space. bits [20:19] apply to configuring the sixth partition in the address space. bits [22:21] apply to configuring the seventh partition in the address space. bits [24:23] apply to configuring the eighth partition in the address space. [71:25] 0 reserved . table 7-4. information register description field range initial value description revision [3:0] 0001 revision number . this is the current device revision number. numbers start at one and increment by one for each revision of the device. implementation [6:4] 001 this is the cynse70128 implementation number. reserved [7] 0 reserved . device id [15:8] 00000100 this is the device identification number. mfid [31:16] 1101_1100_0111_1111 manufacturer id . this field is the same as the manufac- turer identification number and continuation bits in the tap controller. reserved [71:32] reserved . table 7-5. read burst register description field range initial value description adr [15:0] 0 address . this is the starting address of the data or mask array during a burst read operation. it automatically increments by one for each successive read of the data or mask array. once the operation is complete, the contents of this field must be reinitialized for the next operation. [18:16] reserved . blen [27:19] 0 length of burst access . the device provides the capability to read from 4?511 locations in a single burst. the blen decrements automat- ically. once the operation is complete, the contents of this field must be reinitialized for the next operation. [71:28] reserved . table 7-3. command register description (continued) field range initial value description
cynse7012 8 document #: 38-02040 rev. *e page 19 of 137 7.7 write burst address register description table 7-6 describes the write burst address register (wburreg) fields which must be programmed before a burst write. 7.8 nfa register bit [0] of each 72-bit data entry is specially designated for use in the operation of the learn command. for 72-bit-configured quadrants, this bit indicates whether a location is full (bit se t to 1) or empty (bit set to 0). every write and/or learn comma nd loads the address of the first 72-bit location that contains a 0 in the entry?s bit[0]. this is stored in the nfa register (see table 7-7 ). if all the bits[0] in a device are set to 1, the cynse70128 asserts fulo[1:0] to 1. for a 144-bit-configured quadrants, the lsb of the nfa register is always set to 0. the host asic must set both bit[0] and bit[ 72] in a 144-bit word to either 0 or 1 to indicate full or empty status. both bit[0] and bit[72] must be set to either 0 or 1, (tha t is, the 10 or 01 settings are invalid). 8.0 nse architecture and operation overview the cynse70128 consists of 64k 72-bit storage cells referred to as data bits. there is a mask cell corresponding to each data cell. figure 8-1 shows the three organizations of the device based on the value of the cfg bits in the command register. table 7-6. write burst register description field range initial value description adr [15:0] 0 address . this is the starting address of the data or mask array during a burst write operation. it automatically increments by one for each successive write of the data or mask array. once the operation is complete, the contents of this field must be reinitialized for the next operation. [18:16] reserved . blen [27:19] 0 length of burst access . the device provides the capability to write from 4?511 locations in a single burst. the blen decrements automatically. once the operation is complete, the contents of this field must be reinitialized for the next operation. [71:28] reserved . table 7-7. nfa register address 71 ? 16 15 ? 0 60 reserved index data 32 k 144 data masks 16 k 288 cfg = 0101010101010101 cfg = 1010101010101010 data masks 64 k 72 cfg = 0000000000000000 masks figure 8-1. cynse70128 database width configuration
cynse7012 8 document #: 38-02040 rev. *e page 20 of 137 during a search operation, the search data bit (s), data array bit (d), mask array bit (m), and global mask bit (g) are used in the following manner to generate a match at that bit position (see table 8-1 ). the entry with a match on every bit position results in a successful search during a search operation. in order for a successful search within a device to make the device the local winner in the search operation, all 72-bit positi ons must generate a match for a 72-bit entry in 72-bit-configured quadrants, or all 144-bit positions must generate a match for two consecutive even and odd 72-bit entries in quadrants configured as 144 bits, or all 288-bit positions must generate a match for four consecutive entries aligned to four entry-page boundar ies of 72-bit entries in quadrants configured as 288 bits. an arbitration mechanism using a cascade bus determines the global winning device among the local winning devices in a search cycle. the global winning device drives the sram bus, ssv, and the ssf signals. in case of a search failure, the device(s) with the ldev and lram bits set drive(s) the sram bus, ssf, and ssv signals. the cynse70128 device can be configured to contain tables of different widths, even within the same chip. figure 8-2 shows a sample configuration of different widths. table 8-1. bit position match gmd smatch 0xxx1 10xx1 11001 11100 11010 11111
cynse7012 8 document #: 38-02040 rev. *e page 21 of 137 9.0 data and mask addressing figure 9-1 shows cynse70128 data and mask array addressing. 10.0 commands a master device such as an asic controller issues commands to the cynse70128 device using the command valid (cmdv) signal and the cmd bus. the following subsections describe the operation of the commands. 10.1 command codes the cynse70128 implements four basic commands, shown in table 10-1 . the command code must be presented to cmd[1:0] while keeping the cmdv signal high for two clk2x cycles (designated as cycles a and b) when the clk_mode pin is low. in clk2x mode, the controller asic must align the instructions using the phs_l signal. the command code must be presented to cmd[1:0] while keeping the cmdv signal high for one clk1x cycle when the clk_mode pin is high. in clk1x mode the high phase of the clk1x is designated as cycle a and the low phase of the clk1x is designated as cycle b. the cmd[10:2] field passes the parameters of the command in cycles a and b. 4 k 144 2 k 288 8 k 72 8 k 72 8 k 72 8 k 72 4 k 144 2 k 288 inactive (low power) figure 8-2. multiwidth database configurations example cfg = 10 10 01 01 11 11 00 00 cfg = 0000000000000000 cfg = 1010101010101010 71 0 72 0 1 2 3 65535 283 0 72 72 3 2 1 0 7 6 5 4 65532 65533 65534 65535 72 72 cfg = 0101010101010101 143 0 72 72 1 0 3 2 5 4 7 6 65534 65535 (72-bit configuration) (288-bit configuration) (144-bit configuration) 64k 16k 32k figure 9-1. addressing the cynse70128 data and mask arrays
cynse7012 8 document #: 38-02040 rev. *e page 22 of 137 10.2 commands and command parameters table 10-2 lists the cmd bus fields that contain the cynse70128 command parameters and their respective cycles. each command is described separately in the subsections that follow. 10.3 read command the read can be a single read of a data array, a mask array, an sram, or a register location (cmd[2] = 0). it can be a burst read of the data (cmd[2] = 1) or mask array locations usin g an internal auto-incrementing address register (rburadr). a description of each type is provided in table 10-3 . a single-location read operation lasts six cycles, as shown in figure 10-1 . the burst read adds two cycles for each successive read. the sadr[23:21] bits supplied in the read instruction cycle a drives sadr[23:21] signals during the read of an sram location. notes: 8. the 288-bit-configured devices or 288-bit-configured quadrants within devices do not support the learn instruction. also, clk 1x must be less than 8 3mhz. 9. use only cmd[8:0] and connect the cmd[10:9] to ground with cfg_l low. 10. for a description of cmd[9] and cmd[2], see subsections on search 288-bit configured tables and mixed-size searches with cfg _l high. table 10-1. command codes command code command description 00 read reads one of the following: data array, mask array, device registers, or external sram. 01 write writes one of the following: data array, mask array, device registers, or external sram. 10 search searches the data array for a desired pattern using the specified register from the gmr array and local mask associated with each data cell. 11 learn [8] the device has internal storage for up to 16 comparands that it can learn. the device controller can insert these entries at the next free address (as specified by the nfa register) using the learn instruction. table 10-2. command parameters cmd [9, 10] cyc 10 9 8 7 6 5 4 3 2 1 0 read a x x sadr[23] sadr[22] sadr[21] 0 0 0 0 = single 1 = burst 00 b x x 0 0 0 0 0 0 0 = single 1 = burst 00 write a global mask register index [9] 0 normal write 1 parallel write sadr[23] sadr[22] sadr[21] global mask register index [2:0] 0 = single 1 = burst 01 bglobal mask register index [9] 0 normal write 1 parallel write 0 0 0 global mask register index [2:0] 0 = single 1 = burst 01 search a global mask register index [10] 72 bit: 0 144-bit: 1 288 bit: x sadr[23] sadr[22] sadr[21] global mask register index [2:0] 72-bit or 144-bit: 0 288-bit: 1 in 1 st cycle 0 in 2 nd cycle 10 b x successful search register index[2:0] comparand register index 1 0 learn [8] a x x sadr[23] sadr[22] sadr[21] comparand register index 1 1 bx x 0 0 mode 0: 72-bit 1: 144-bit comparand register index 1 1
cynse7012 8 document #: 38-02040 rev. *e page 23 of 137 the single read operation takes six clock cycles, in the following sequence. cycle 1 : the host asic applies the read instruction on the cmd[1:0] (cmd[2]= 0) using cmdv = 1 and the dq bus supplies the address, as shown in table 10-4 and table 10-5 . the host asic selects the cynse70128 for which id[4:0] matches the dq[25:21] lines. if the dq[25:21] = 11111, the host asic selects the cynse70128 with the ldev bit set. the host asic also supplies sadr[23:21] on cmd[8:6] in cycle a of the read instruction if the read is directed to the external sram. cycle 2 : the host asic floats dq[71:0] to three-state condition. cycle 3 : the host asic keeps dq[71:0] in three-state condition. cycle 4 : the selected device starts to drive the dq[71:0] bus, and drives the ack signal from z to low. cycle 5 : the selected device drives the read data from the addressed location on the dq[71:0] bus, and drives the ack signal high. cycle 6 : the selected device floats the dq[71:0] to three-state condition and drives the ack signal low. at the termination of cycle 6, the selected device releases the ack line to three-state condition. the read instruction is comp lete, and a new operation can begin. note . the latency of the sram read will be different than the one described above (see ?sram pio access? on page 106). table 10-4 lists and describes the format of the read address for a data array, mask array, or sram. table 10-3. read command parameters cmd parameter cmd[2] read command description 0 single read reads a single location of the data array, mask array, external sram, or device registers. all access information is applied on the dq bus. 1 burst read reads a block of locations from the data array, or mask array as a burst. the internal register (rburadr) specifies the starting address and the length of the data transfer from the data or mask arra y, and it auto-increments the address for each access. all other access information is applied on the dq bus. note . the device registers and external sram can only be read in single-read mode. table 10-4. read address format for data array, mask array, or sram dq[71:30] dq[29] dq[28:26] dq[25:21] dq[20:19] dq[18:16] dq[15:0] reserved 0: direct 1: indirect successful search register index (appli- cable if dq[29] is indirect) id 00: data array reserved if dq[29] is 0, this field carries the address of the data array location. if dq[29] is 1, the ssri specified on dq[28:26] is used to generate the address of the data array location: {ssr[15:2], ssr[1] | dq[1], ssr[0] | dq[0]}. [11] note: 11. ?|? stands for logical or operation. ?{}? stands for concatenation operator. cycle cycle cycle cycle cycle cycle read address ff data 1 2 345 6 clk2x cmdv cmd[1:0] ack dq cmd[10:2] a b phs_l figure 10-1. single-location read cycle timing
cynse7012 8 document #: 38-02040 rev. *e page 24 of 137 table 10-5 describes the read address format for the internal registers. figure 10-2 illustrates the timing diagram for the burst read of the data or mask array. the read operation lasts 4 + 2n clk cycles (where n is the number of accesses in the burst specified by the blen field of the rburreg) in the sequence shown below. this operation assumes that the host asic has programmed the rburreg with the starting address (adr) and the length of the transfer (blen) before initiating the burst read command. cycle 1 : the host asic applies the read instruction on cmd[1:0] (cmd[2] = 1) using cmdv = 1 and the address supplied on the dq bus, as shown in table 10-6 . the host asic selects the cynse70128 where id[4:0] matches the dq[25:21] lines. if the dq[25:21] = 11111, the host asic selects the cynse70128 with the ldev bit set. cycle 2 : the host asic floats dq[71:0] to the three-state condition. cycle 3 : the host asic keeps dq[71:0] in the three-state condition. cycle 4 : the selected device starts to drive the dq[71:0] bus and drives ack and eot from z to low. cycle 5 : the selected device drives the read data from the addressed location on the dq[71:0] bus, and drives the ack signal high. cycles 4 and 5 repeat for each additional access until all the accesses specified in the burst length (blen) field of rburreg are complete. on the last transfer, the cynse70128 drives the eot signal high. cycle (4 + 2n) : the selected device drives the dq[71:0] to the three-state condition, and drives the ack and eot signals low. at the termination of cycle (4 + 2n), the selected device floats the ack line to the three-state condition. the burst read inst ruction is complete, and a new operation can begin. table 10-6 describes the read address format for data and mask arrays for burst read operations. reserved 0: direct 1: indirect successful search register index (appli- cable if dq[29] is indirect) id 01: mask array reserved if dq[29] is 0, this field carries the address of the mask array location. if dq[29] is 1, the ssri specified on dq[28:26] is used to generate the address of the mask array location: {ssr[15:2], ssr[1] | dq[1], ssr[0] | dq[0]}. [11] reserved 0: direct 1: indirect successful search register index (appli- cable if dq[29] is indirect) id 10: external sram reserved if dq[29] is 0, this field carries the address of the sram location. if dq[29] is 1, the ssri specified on dq[28:26] is used to generate the address of the sram location: {ssr[15:2], ssr[1] | dq[1], ssr[0] | dq[0]}. [11] table 10-5. read address format for internal registers dq[71:26] dq[25:21] dq[20:19] dq[18:7] dq[6:0] reserved id 11: register reserved register address table 10-4. read address format for data array, mask array, or sram (continued) dq[71:30] dq[29] dq[28:26] dq[25:21] dq[20:19] dq[18:16] dq[15:0] cmdv cmd[1:0] ack eot dq ff ff data1 cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 cycle 11 cycle 12 data0 data2 ff data3 ff phs_l cmd[10:2] address a b read clk2x figure 10-2. burst read of the data and mask arrays (blen = 4)
cynse7012 8 document #: 38-02040 rev. *e page 25 of 137 10.4 write command the write can be a single write of a data array, mask array, register, or external sram location (cmd[2] = 0). it can be a burs t write (cmd[2] = 1) using an internal auto-incrementing address register (wburadr) of the data or mask array locations. a single-location write is a three-cycle operation, as shown in figure 10-3 . the burst write adds one extra cycle for each successive location write. the following is the write operation sequence, and table shows the write address format for the data array, the mask array, or the single-write sram. table 10-8 shows the write address format for the internal registers. cycle 1a : the host asic applies the write instruction to the cmd[1:0] (cmd[2] = 0), using cmdv = 1 and the address supplied on the dq bus. the host asic also supplies the gmr index to mask the write to the data or mask array location on {cmd[10],cmd[5:3]}. for sram writes, the host asic must supply the sadr[23:21] on cmd[8:6]. the host asic sets cmd[9] to 0 for the normal write. cycle 1b :the host asic continues to apply the write instruction to the cmd[1:0] (cmd[2] = 0), using cmdv = 1 and the address supplied on the dq bus. the host asic continues to supply the gmr index to mask the write to the data or mask array locations in {cmd[10], cmd[5:3]}.the host asic selects the device where id[4:0] matches the dq[25:21] lines, or it selects all the devices when dq[25:21] = 11111. cycle 2 : the host asic drives the dq[71:0] with the data to be written to the data array, mask array, or register location of the selected device. cycle 3 : idle cycle. at the termination of cycle 3, another operation can begin. note . the latency of the sram write will be different than the one described above (see ?sram pio access? on page 106). table 10-6. read address format for data and mask arrays dq[71:26] dq[25:21] dq[20:19] dq[18:16] dq[15:0] reserved id 00: data array reserved do not care . these 16 bits come from the internal register (rburadr) which increments for each access. reserved id 01: mask array reserved do not care . these 16 bits come from the internal register (rburadr) which increments for each access. cycle 2 cycle 3 write address data cmdv cmd[1:0] dq x cycle 1 cycle 0 cycle 4 cmd[10:2] b phs_l a clk2x figure 10-3. single write cycle timing
cynse7012 8 document #: 38-02040 rev. *e page 26 of 137 a figure 10-4 shows the timing diagram of a burst write operation of the data or mask array. the burst write operation lasts for (n + 2) clk cycles. n signifies the number of accesses in the burst as specified in the ble n field of the wburreg register. the following is the block write operation sequence. this operation assumes that the host asic has programmed the wburreg with the starting address (adr) and the length of transfer (blen) before initiating a burst write command. cycle 1a : the host asic applies the write instruction to the cmd[1:0] (cmd[2] = 1), using cmdv = 1 and the address supplied on the dq bus, as shown in table 10-9 . the host asic also supplies the gmr index to mask the write to the data or mask array locations in {cmd[10], cmd[5:3]}. the host asic sets cmd[9] to 0 for the normal write. cycle 1b : the host asic continues to apply the write instruction on the cmd[1:0] (cmd[2] = 1), using cmdv = 1 and the address supplied on the dq bus. the host asic continues to supply the gmr index to mask the write to the data or mask array locations in {cmd[10], cmd[5:3]}. the host asic selects the device for which id[4:0] matches the dq[25:21] lines. it selects all the devices when dq[25:21] = 11111. cycle 2 : the host asic drives the dq[71:0] with the data to be written to the data or mask array location of the selected device. the cynse70128 writes the data from the dq[71:0] bus only to the subfield that has the corresponding mask bit set to 1 in the gmr specified by the index {cmd[10],cmd[5:3]} supplied in cycle 1. note: 12. ?|? stands for logical or operation. ?{}? stands for concatenation operator. table 10-7. write address format for data array, mask array or sram (single write) dq[71:30] dq[29] dq[28:26] dq[25:2 1] dq[20:19] dq[18:16] dq[15:0] reserved 0: direct 1: indirect ssr (appli- cable if dq[29] is indirect) id 00: data array reserved if dq[29] is 0, this field carries the address of the data array location. if dq[29] is 1, the ssr specified on dq[28:26] is used to generate the address of data array location: {ssr[15:2], ssr[1] | dq[1], ssr[0] | dq[0]} [ figure 10-4 ]. [12] reserved 0: direct 1: indirect ssr (appli- cable if dq[29] is indirect) id 01: mask array reserved if dq[29] is 0, this field carries the address of the mask array location. if dq[29] is 1, the ssr specified on dq[28:26] is used to generate the address of the mask array location: {ssr[15:2], ssr[1] | dq[1], ssr[0] | dq[0]} [ figure 10-4 ]. reserved 0: direct 1: indirect ssr (appli- cable if dq[29] is indirect) id 10: external sram reserved if dq[29] is 0, this field carries the address of the sram location. if dq[29] is 1, the ssr specified on dq[28:26] is used to generate the address of sram location: {ssr[15:2], ssr[1] | dq[1], ssr[0] | dq[0]} [ figure 10-4 ]. table 10-8. write address format for internal registers dq[71:26] dq[25:21] dq[20:19] dq[18:7] dq[6:0] reserved id 11: register reserved register address 1 data0 data1 data2 x data3 write address cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle cmd[1:0] dq clk2x eot cmd[10:2] a b phs_l cmdv figure 10-4. burst write of the data and mask arrays (blen = 4)
cynse7012 8 document #: 38-02040 rev. *e page 27 of 137 cycles 3 to n + 1 : the host asic drives the dq[71:0] with the data to be written to the next data or mask array location (addressed by the auto-increment adr field of the wburreg register) of the selected device. the cynse70128 writes the data on the dq[71:0] bus only to the subfield that has the corresponding mask bit set to 1 in the gmr specified by the index {cmd[10],cmd[5:3]} supplied in cycle 1. the cynse70128 drives the eot signal low from cycle 3 to cycle n; the cynse70128 drives the eot signal high in cycle n + 1 (n is specified in the blen field of the wburreg). cycle n + 2 : thecynse70128 drives the eot signal low. at the termination of cycle n + 2, the cynse70128 floats the eot signal to a three-state operation, and a new instruction can begin. 10.5 parallel write in order to write the data and mask arrays faster for initialization, testing, or diagnostics, many locations can be written si multa- neously in the cynse70128 device. when cmd[9] is set in cycles a and b of the write command during a write to the data or mask arrays, the address present on dq[10:1] that specifies 64 locations in a device is used and 64 72-bit locations are simul- taneously written in either the data or mask array. 10.6 search command this subsection describes the following: 72-bit search on tables configured as 72 using one device 72-bit search on tables configured as 72 using up to eight devices 72-bit search on tables configured as 72 using up to 31 devices 144-bit search on tables configured as 144 using one device 144-bit search on tables configured as 144 using up to eight devices 144-bit search on tables configured as 144 using up to 31 devices 288-bit search on tables configured as 288 using one device 288-bit search on tables configured as 288 using up to eight devices 288-bit search on tables configured as 288 using up to 31 devices mixed-size searches on tables configured with different widths using an cynse70128 with cfg_l low mixed-size searches on tables configured with different widths using an cynse70128 with cfg_l high. 10.6.1 72-bit search on tables configured as 72 using a single cynse70128 device figure 10-5 shows the timing diagram for a search command in the 72-bit-configured table (cfg = 0000000000000000) consisting of a single device for one set of parameters: tlsz = 00, hlat = 000, lram = 1, ldev = 1. the hardware diagram for this search subsystem is shown in figure 10-6 . table 10-9. write address format for data and mask array (burst write) dq[71:26] dq[25:21] dq[20:19] dq[18:16] dq[15:0] reserved id 00: data array reserved do not care . these 16 bits come from the internal register (wburadr), which increments with each access. reserved id 01: mask array reserved do not care . these 16 bits come from the internal register (wburadr), which increments with each access.
cynse7012 8 document #: 38-02040 rev. *e page 28 of 137 the following is the sequence of operation for a single 72-bit search command (also refer to ?command and command param- eters,? subsection 10.2 on page 22). cycle a : the host asic drives the cmdv high and applies search command code (10) on cmd[1:0] signals. {cmd[10], cmd[5:3]} signals must be driven with the index to the gmr pair for use in this search operation. cmd[8:6] signals must be driven with the same bits that will be driven on sadr[23:21] by this device if it has a hit. dq[71:0] must be driven with the 72-bit data to be compared. the cmd[2] signal must be driven to logic 0. cycle b : the host asic continues to drive the cmdv high and to apply search command (10) on cmd[1:0]. cmd[5:2] must be driven by the index of the comparand register pair for storing the 144-bit word presented on the dq bus during cycles a cycle clk2x cmdv cmd[1:0] dq ce_l oe_l hit hit miss miss cmd[10:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 c fg = 0000000000000000, hlat = 000, tlsz = 00, lram = 1, ldev = 1. phs_l sadr[23:0] ssf ssv ale_l search1 search2 search3 search4 d1 d2 d3 d4 a1 a3 01 01 01 01 search1 search3 a b a b a b a b 0 1 0 0 1 1 0 1 1 0 0 0 1 0 1 1 0 1 1 0 0 0 1 0 0 1 1 1 figure 10-5. timing diagram for 72-bit search in x72 table (one device) lho[0] 6543210 lhi lho[1] bhi[2:0] dq[71:0] sram cynse70128 cmdv, cmd10:0] bhi[2:0] ssf, ssv figure 10-6. hardware diagram for a table with one device
cynse7012 8 document #: 38-02040 rev. *e page 29 of 137 and b. cmd[8:6] signals must be driven with the index of the ssr that will be used for storing the address of the matching entry and the hit flag (see page 8 for information on ssr[0:7]). the dq[71:0] continues to carry the 72-bit data to be compared . note . for 72-bit searches, the host asic must supply the same 72-bit data on dq[71:0] during both cycles a and b. the even and odd pair of gmrs selected for the compare must be programmed with the same value. the logical 72-bit search operation is shown in figure 10-7 . the entire table consisting of 72-bit entries is compared to a 72-bit word k (presented on the dq bus in both cycles a and b of the command) using the gmr and the local mask bits. the effective gmr is the 72-bit word specified by the identical value in both even and odd gmr pairs selected by the gmr index in the command?s cycle a. the 72-bit word k (presented on the dq bus in both cycles a and b of the command) is also stored in both even and odd comparand register pairs selected by the comparand register index in the command?s cycle b. in a 72 configu- ration, only the even comparand register can be subsequently used by the learn command. the word k (presented on the dq bus in both cycles a and b of the command) is compared with each entry in the table starting at location 0. the first matching entry?s location address l is the winning address that is driv en as part of the sram address on the sadr[23:0] lines (see ?sram addressing? on page 105). the search command is a pipelined operation and executes a search at half the rate of the frequency of clk2x for 72-bit searches in 72-configured tables. the latency of sadr, ce_l, ale_l, we_l, ssv, and ssf from the 72-bit search command cycle (two clk2x cycles) is shown in table 10-10 . the latency of a search from command to sram access cycle is 4 for a single device in the table and tlsz = 00. in addition, ssv and ssf shift further to the right for different values of hlat, as specified in table 10-11 . table 10-10. the latency of search from instruction to sram access cycle number of devices max table size latency in clk cycles 1 (tlsz = 00) 64k 72 bits 4 1?8 (tlsz = 01) 512k 72 bits 5 1?31 (tlsz = 10) 1984k 72 bits 6 table 10-11. shift of ssf and ssv from sadr hlat number of clk cycles 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 cfg = 0000000000000000 71 0 location 0 1 2 3 65535 (288-bit configuration) address k gmr comparand register (odd) comparand register (even) k k 71 0 71 0 (first matching entry) l figure 10-7. x72 table with one device
cynse7012 8 document #: 38-02040 rev. *e page 30 of 137 10.6.2 72-bit search on tables configured as 72 using up to eight cynse70128 devices the hardware diagram of the search subsystem of eight devices is shown in figure 10-8 . the following are the parameters programmed into the eight devices. first seven devices (device 0?6): cfg = 0000000000000000, tlsz = 01, hlat = 010, lram = 0, and ldev = 0. eighth device (device 7): cfg = 0000000000000000, tlsz = 01, hlat = 010, lram = 1, and ldev = 1. note . all eight devices must be programmed with the same values for tlsz and hlat. only the last device in the table (device number 7 in this case) must be programmed with lram = 1 and ldev = 1. all other upstream devices (devices 0 through 6 in this case) must be programmed with lram = 0 and ldev = 0. figure 10-9 shows the timing diagram for a search command in the 72-bit-configured table of eight devices for device number 0. figure 10-10 shows the timing diagram for a search command in the 72-bit-configured table of eight devices for device number 1. figure 10-11 shows the timing diagram for a search command in the 72-bit-configured table of eight devices for device number 7 (the last device in this specific table). for these timing diagrams four 72-bit searches are performed sequentially. hit/miss a ssump- tions were made as shown below in table 10-12 . table 10-12. hit/miss assumption search number 1 2 3 4 device 0 hit miss hit miss device 1 miss hit hit miss device 2?6missmissmissmiss device 7 miss miss hit hit
cynse7012 8 document #: 38-02040 rev. *e page 31 of 137 lho[0] 6543210 lhi lho[0] 65 32 10 lhi lho[1] 6543 210 lhi lho[0] 654321 0 lhi lho[0] 654 3210 lhi lho[0] 65 4 3210 lhi lho[0] 654 32 10 lhi bho[0] 654 3 210 lhi lho[0] lhi lhi lhi lho[1] lho[1] lho[1] bho[1] bho[0] bho[1] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] dq[71:0] sram lho[1] lho[0] cynse70128 #0 cynse70128 #1 cynse70128 #2 cynse70128 #3 cynse70128 #4 cynse70128 #5 cynse70128 #6 cynse70128 #7 4 bho[2] bho[2] cmdv cmd[10:0] ssf, ssv figure 10-8. hardware diagram for a table with eight devices
cynse7012 8 document #: 38-02040 rev. *e page 32 of 137 cycle clk2x cmdv cmd[1:0] dq ce_l oe_l (this device cmd[10:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 cfg = 0000000000000000, hlat = 010, tlsz = 01, lram = 0, ldev = 0. note: |(lhi[6:0]) stands for the boolean ?or? of the entire bus lhi[6:0]. note: each bit in lho[1:0] is the same logical signal. phs_l sadr[23:0] ssf ssv ale_l search1 search4 d1 d2 d3 d4 01 01 01 01 search1 search3 a b a b a b a b a1 a3 z z z z z z z z z z z z z z z 0 0 1 0 0 1 1 1 1 1 z z z z is the global winner.) (this device is the global winner.) |(lhi[6:0]) 0 (miss on this device.) lho[1:0] search2 (miss on this device.) search3 figure 10-9. timing diagram for 72-bit search device number 0
cynse7012 8 document #: 38-02040 rev. *e page 33 of 137 cycle clk2x cmdv cmd[1:0] dq ce_l oe_l (miss cmd[10:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 cfg = 0000000000000000, hlat = 010, tlsz = 01, lram = 0, ldev = 0. note: |(lhi[6:0]) stands for the boolean ?or? of the entire bus lhi[6:0]. note: each bit in lho[1:0] is the same logical signal. phs_l sadr[23:0] ssf ssv ale_l search1 search2 search3 search4 d1 d2 d3 d4 01 01 01 01 search1 search3 a b a b a b a b a2 z z z z 1 1 z z (local winner but not global winner.) (miss on this device.) |(lhi[6:0]) lho[1:0] z 0 z z 0 z z 1 z on this device.) (this device is global winner.) figure 10-10. timing diagram for 72-bit search device number 1
cynse7012 8 document #: 38-02040 rev. *e page 34 of 137 the following is the sequence of operation for a single 72-bit search command (also refer to ?command and command param- eters,? subsection 10.2 on page 22). cycle a : the host asic drives the cmdv high and applies search command code (10) to cmd[1:0] signals. {cmd[10], cmd[5:3]} signals must be driven with the index to the gmr pair for use in this search operation. cmd[8:6] signals must be driven with the same bits that will be driven on sadr[23:21] by this device if it has a hit. dq[71:0] must be driven with the 7 2- bit data to be compared. the cmd[2] signal must be driven to logic 0. cycle b : the host asic continues to drive the cmdv high and to apply search command (10) on cmd[1:0]. cmd[5:2] must be driven by the index of the comparand register pair for storing the 144-bit word presented on the dq bus during cycles a and b. cmd[8:6] signals must be driven with the index of the ssr that will be used for storing the address of the matching entry and hit flag (see page 8 for a description of ssr[0:7]). the dq[71:0] continues to carry the 72-bit data to be compared. cycle clk2x cmdv cmd[1:0] dq ce_l oe_l (miss cmd[10:2] search2 search4 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 c fg = 0000000000000000, hlat = 010, tlsz = 01, lram = 1, ldev = 1. n ote: |(lhi[6:0]) stands for the boolean ?or? of the entire bus lhi[6:0]. n ote: each bit in lho[1:0] is the same logical signal. phs_l sadr[23:0] ssf ssv search1 search2 search3 d1 d2 d3 d4 01 01 01 01 search1 search3 a b a b a b a b a4 0 (local but not global winner) |(lhi[6:0]) lho[1:0] on this device .) (miss on this device) 0 z 0 0 z 0 ale_l we_l 1z 1 0 z 1 0 0 z 1 0 search4 (global winner) z figure 10-11. timing diagram for 72-bit search device number 7 (last device)
cynse7012 8 document #: 38-02040 rev. *e page 35 of 137 note . for 72-bit searches, the host asic must supply the same 72-bit data on dq[71:0] during both cycles a and b, and the even and odd pairs of gmrs selected for the comparison must be programmed with the same value. the logical 72-bit search operation is shown in figure 10-12 . the entire table with eight devices of 72-bit entries is compared to a 72-bit word k (presented on the dq bus in both cycles a and b of the command) using the gmr and the local mask bits. the effective gmr is the 72-bit word specified by the identical value in both even and odd gmr pairs in each of the eight devices a nd selected by the gmr index in the command?s cycle a. the 72-bit word k (presented on the dq bus in both cycles a and b of the command) is also stored in both even and odd comparand register pairs (selected by the comparand register index in command cycle b) in each of the eight devices. in the 72 configuration, only the even comparand register can subsequently be used by the learn command in one of the devices (only the first non-full device). the word k (presented on the dq bus in both cycles a and b of the command) is compared with each entry in the table starting at location 0. the first matching entry?s location addr ess l is the winning address that is driven as part of the sram address on the sadr[23:0] lines (see ?sram addressing? on page 105). the global winning device will drive the bus in a specific cycle. on a global miss cycle the device with lram = 1 (default driving device for the sram bus) and ldev = 1 (default driving device for ssf and ssv signals) will be the default drive r for such missed cycles. the search command is a pipelined operation and executes a search at half the rate of the frequency of clk2x for 72-bit searche s in x72-configured tables. the latency of sadr, ce_l, ale_l, we_l, ssv, and ssf from the 72-bit search command cycle (two clk2x cycles) is shown in table 10-13 . the latency of the search from command to sram access cycle is 5 for up to eight devices in the table (tlsz = 01). ssv and ssf also shift further to the right for different values of hlat, as specified in table 10-14 . table 10-13. the latency of search from instruction to sram access cycle number of devices max table size latency in clk cycles 1 (tlsz = 00) 64k 72 bits 4 1?8 (tlsz = 01) 512k 72 bits 5 1?31 (tlsz = 10) 1984k 72 bits 6 table 10-14. shift of ssf and ssv from sadr hlat number of clk cycles 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 cfg = 0000000000000000 71 0 location 0 1 2 3 524287 (72-bit configuration) address k gmr comparand register (odd) comparand register (even) k k 71 0 71 0 (first matching entry) l must be same in each of the eight devices will be same in each of the eight devices figure 10-12. x72 table with eight devices
cynse7012 8 document #: 38-02040 rev. *e page 36 of 137 10.6.3 72-bit search on tables configured as x72 using up to 31 cynse70128 devices the hardware diagram of the search su bsystem of 31 devices is shown in figure 10-13 . each of the four blocks in the diagram represents eight cynse70128 devices (except the last, which has seven devices). the diagram for a block of eight devices is shown in figure 10-14 . the following are the parameters programmed into the 31 devices. first thirty devices (devices 0?29): cfg = 0000000000000000, tlsz = 10, hlat = 001, lram = 0, and ldev = 0. thirty-first device (device 30): cfg = 0000000000000000, tlsz = 10, hlat = 001, lram = 1, and ldev = 1. note . all 31 devices must be programmed with the same values for tlsz and hlat. only the last device in the table must be programmed with lram = 1 and ldev = 1 (device number 30 in this case). all other upstream devices must be programmed with lram = 0 and ldev = 0 (devices 0 through 29 in this case). the timing diagrams referred to in this paragraph reference the hit/miss assumptions defined in table 10-15 . for the purpose of illustrating the timings, it is further assumed that the there is only one device with a matching entry in each of the blocks. figure 10- 15 shows the timing diagram for a search command in the 72-bit-configured table of 31 devices for each of the eight devices in block 0. figure 10-16 shows a timing diagram for a search command in the 72-bit-configured table of 31 devices for the all the devices in block number 1 (above the winning device in that block). figure 10-17 shows the timing diagram for the globally winning device (defined as the final winner within its own and all blocks) in block number 1. figure 10-18 shows the timing diagram for all the devices below the globally winning device in block number 1. figure 10-19 , figure 10-20 , and figure 10-21 show the timing diagrams of the devices above the globally winning device, the globally winning device, and the devices below the globally winn ing device, respectively, for block number 2. figure 10-22 , figure 10-23 , figure 10-24 , and figure 10-25 show the timing diagrams of the devices above globally winning device, the globally winning device, and the devices below the globally winning device except the last device (device 30), respectively, for block number 3. the 72-bit search operation is pipelined and executes as follows. four cycles from the search command, each of the devices knows the outcome internal to it for that operation. in the fifth cycle after the search command, the devices in a block arbitr ate for a winner amongst them (a ?block? being defined as less than or equal to eight devices resolving the winner within them usin g the lhi[6:0] and lho[1:0] signalling mechanism). in the sixth cycle after the search command, the blocks (of devices) resolve the winning block through the bhi[2:0] and bho[2:0] signalling mechanism. the winning device within the winning block is the global winning device for a search operation. table 10-15. hit/miss assumption search number 1 2 3 4 block 0missmissmissmiss block 1 miss miss hit miss block 2 miss hit hit miss block 3 hit hit miss miss
cynse7012 8 document #: 38-02040 rev. *e page 37 of 137 bho[2] block of 8 cynse70128s block 0 (devices 0?7) bho[1] bho[0] bhi[2] bhi[1] bhi[0] bhi[2] block of 7 cynse70128s block 3 (devices 24?30) bhi[1] bhi[0] gnd bho[2] bho[1] bho[0] bhi[2] bhi[1] bhi[0] gnd bhi[2] bhi[1] bhi[0] gnd block of 8 cynse70128s block 1 (devices 8?15) block of 8 cynse70128s block 2 (devices 16?23) dq[71:0] sram bho[2] bho[2] bho[1] bho[1] bho[0] bho[0] cmd[10:0], cmdv ssf, ssv figure 10-13. hardware diagram for a table with 31 devices
cynse7012 8 document #: 38-02040 rev. *e page 38 of 137 lho[0] 6543210 lhi lho[0] 65 32 10 lhi lho[1] 6543 210 lhi lho[0] 654321 0 lhi lho[0] 654 3210 lhi lho[0] 65 4 3210 lhi lho[0] 654 32 10 lhi bho[0] 654 3 210 lhi lho[0] lhi lhi lhi lho[1] lho[1] lho[1] bho[1] bho[0] bho[1] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] dq[71:0] sram lho[1] lho[0] cynse70128 #0 cynse70128 #1 cynse70128 #2 cynse70128 #3 cynse70128 #4 cynse70128 #5 cynse70128 #7 4 bho[2] bho[2] cmdv cmd[10:0] bhi[2:0] ssv, ssf cynse70128 #6 figure 10-14. hardware diagram for a block of up to eight devices
cynse7012 8 document #: 38-02040 rev. *e page 39 of 137 cycle clk2x cmdv cmd[1:0] dq ce_l oe_l cmd[10:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 c fg = 0000000000000000, hlat = 001, tlsz = 10, lram = 0, ldev = 0. n ote: |(bhi[2:0]) stands for the boolean ?or? of the entire bus bhi[2:0]. n ote: |(lhi[6:0]) stands for the boolean ?or? for the entire bus lhi[6:0]. n ote: each bit in bho[2:0] is the same logical signal. n ote: each bit in lho[1:0] is the same logical signal. phs_l sadr[23:0] ssf ssv ale_l search1 search2 search4 d1 d2 d3 d4 01 01 01 01 search1 search3 a b a b a b a b z z z z z z z lho[1:0] 0 (miss on this device.) (miss on this device.) i(bhi[2:0]) 0 (miss on this device.) search3 (miss on this device.) |(lhi[6:0]) 0 bho[2:0] 0 figure 10-15. timing diagram for each device in block number 0 (miss on each device)
cynse7012 8 document #: 38-02040 rev. *e page 40 of 137 cycle clk2x cmdv cmd[1:0] dq ce_l oe_l cmd[10:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 c fg = 0000000000000000, hlat = 001, tlsz = 10, lram = 0, ldev = 0. n ote: |(bhi[2:0)] stands for the boolean ?or? of the entire bus bhi[2:0]. n ote: |(lhi[6:0]) stands for the boolean ?or? for the entire bus lhi[6:0]. n ote: each bit in bho[2:0] is the same logical signal. n ote: each bit in lho[1:0] is the same logical signal. phs_l sadr[23:0] ssf ssv ale_l search1 search2 search4 d1 d2 d3 d4 01 01 01 01 search1 search3 a b a b a b a b z z z z z z z lho[1:0] 0 (miss on this device.) (miss on this device.) i(bhi[2:0]) 0 (miss on this device.) search3 (miss on this device.) |(lhi[6:0]) 0 bho[2:0] 0 figure 10-16. timing diagram for each device above the winning device in block number 1
cynse7012 8 document #: 38-02040 rev. *e page 41 of 137 cycle clk2x cmdv cmd[1:0] dq ce_l oe_l cmd[10:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 c fg = 0000000000000000, hlat = 001, tlsz = 10, lram = 0, ldev = 0. n ote: |(bhi[2:0]) stands for the boolean ?or? of the entire bus bhi[2:0]. n ote: |(lhi[6:0]) stands for the boolean ?or? for the entire bus lhi[6:0]. n ote: each bit in bho[2:0] is the same logical signal. n ote: each bit in lho[1:0] is the same logical signal. phs_l sadr[23:0] ssf ssv ale_l search1 search2 search4 d1 d2 d3 d4 01 01 01 01 search1 search3 a b a b a b a b z z z z z z z lho[1:0] 0 (miss on this device.) (miss on this device.) i(bhi[2:0]) 0 (miss on this device.) search3 (this device global winner.) |(lhi[6:0]) 0 bho[2:0] 0 a3 z z z z z z figure 10-17. timing diagram for globally winning device in block number 1
cynse7012 8 document #: 38-02040 rev. *e page 42 of 137 cycle clk2x cmdv cmd[1:0] dq ce_l oe_l cmd[10:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 c fg = 0000000000000000, hlat = 001, tlsz = 10, lram = 0, ldev = 0. n ote: |(bhi[2:0]) stands for the boolean ?or? of the entire bus bhi[2:0]. n ote: |(lhi[6:0]) stands for the boolean ?or? for the entire bus lhi[6:0]. n ote: each bit in bho[2:0] is the same logical signal. n ote: each bit in lho[1:0] is the same logical signal. phs_l sadr[23:0] ssf ssv ale_l search1 search2 search4 d1 d2 d3 d4 01 01 01 01 search1 search3 a b a b a b a b z z z z z z z lho[1:0] 0 (miss on this device.) (miss on this device.) i(bhi[2:0]) 0 (miss on this device.) search3 (miss on this device.) |(lhi[6:0]) 0 bho[2:0] 0 figure 10-18. timing diagram for devices below the winning device in block number 1
cynse7012 8 document #: 38-02040 rev. *e page 43 of 137 cycle clk2x cmdv cmd[1:0] dq ce_l oe_l cmd[10:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 c fg = 0000000000000000, hlat = 001, tlsz = 10, lram = 0, ldev = 0. n ote: |(bhi[2:0]) stands for the boolean ?or? of the entire bus bhi[2:0]. n ote: |(lhi[6:0]) stands for the boolean ?or? for the entire bus lhi[6:0]. n ote: each bit in bho[2:0] is the same logical signal. n ote: each bit in lho[1:0] is the same logical signal. phs_l sadr[23:0] ssf ssv ale_l search1 search2 search4 d1 d2 d3 d4 01 01 01 01 search1 search3 a b a b a b a b z z z z z z z lho[1:0] 0 (miss on this device.) (miss on this device.) i(bhi[2:0]) 0 (miss on this device.) search3 (miss on this device.) |(lhi[6:0]) 0 bho[2:0] 0 figure 10-19. timing diagram for devices above the winning device in block number 2
cynse7012 8 document #: 38-02040 rev. *e page 44 of 137 cycle clk2x cmdv cmd[1:0] dq ce_l oe_l cmd[10:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 c fg = 0000000000000000, hlat = 001, tlsz = 10, lram = 0, ldev = 0. n ote: |(bhi[2:0]) stands for the boolean ?or? of the entire bus bhi[2:0]. n ote: |(lhi[6:0]) stands for the boolean ?or? for the entire bus lhi[6:0]. n ote: each bit in bho[2:0] is the same logical signal. n ote: each bit in lho[1:0] is the same logical signal. phs_l sadr[23:0] ssf ssv ale_l search1 search2 search4 d1 d2 d3 d4 01 01 01 01 search1 search3 a b a b a b a b z z z z z z lho[1:0] 0 (global winner.) (miss on this device.) i(bhi[2:0]) 0 (miss on this device.) search3 (hit but not winner.) |(lhi[6:0]) 0 bho[2:0] 0 a2 0 z 0 1 1 1 z z z z z z figure 10-20. timing diagram for globally winning device in block number 2
cynse7012 8 document #: 38-02040 rev. *e page 45 of 137 cycle clk2x cmdv cmd[1:0] dq ce_l oe_l cmd[10:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 c fg = 0000000000000000, hlat = 001, tlsz = 10, lram = 0, ldev = 0. n ote: |(bhi[2:0]) stands for the boolean ?or? of the entire bus bhi[2:0]. n ote: |(lhi[6:0]) stands for the boolean ?or? for the entire bus lhi[6:0]. n ote: each bit in bho[2:0] is the same logical signal. n ote: each bit in lho[1:0] is the same logical signal. phs_l sadr[23:0] ssf ssv ale_l search1 search2 search4 d1 d2 d3 d4 01 01 01 01 search1 search3 a b a b a b a b z z z z z z lho[1:0] 0 (miss on this device.) (miss on this device.) i(bhi[2:0]) 0 (miss on this device.) search3 (miss on this device.) |(lhi[6:0]) 0 bho[2:0] 0 z figure 10-21. timing diagram for devices below the winning device in block number 2
cynse7012 8 document #: 38-02040 rev. *e page 46 of 137 cycle clk2x cmdv cmd[1:0] dq ce_l oe_l cmd[10:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 c fg = 0000000000000000, hlat = 001, tlsz = 10, lram = 0, ldev = 0. n ote: |(bhi[2:0]) stands for the boolean ?or? of the entire bus bhi[2:0]. n ote: |(lhi[6:0]) stands for the boolean ?or? for the entire bus lhi[6:0]. n ote: each bit in bho[2:0] is the same logical signal. n ote: each bit in lho[1:0] is the same logical signal. phs_l sadr[23:0] ssf ssv ale_l search1 search2 search4 d1 d2 d3 d4 01 01 01 01 search1 search3 a b a b a b a b z z z z z z lho[1:0] 0 (miss on this device.) (miss on this device.) i(bhi[2:0]) 0 (miss on this device.) search3 (miss on this device.) |(lhi[6:0]) 0 bho[2:0] 0 z figure 10-22. timing diagram for devices above the winning device in block number 3
cynse7012 8 document #: 38-02040 rev. *e page 47 of 137 cycle clk2x cmdv cmd[1:0] dq ce_l oe_l cmd[10:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 c fg = 0000000000000000, hlat = 001, tlsz = 10, lram = 0, ldev = 0. n ote: |(bhi[2:0]) stands for the boolean ?or? of the entire bus bhi[2:0]. n ote: |(lhi[6:0]) stands for the boolean ?or? for the entire bus lhi[6:0]. n ote: each bit in bho[2:0] is the same logical signal. n ote: each bit in lho[1:0] is the same logical signal. phs_l sadr[23:0] ssf ssv ale_l search1 search2 search4 d1 d2 d3 d4 01 01 01 01 search1 search3 a b a b a b a b z z z z z z lho[1:0] 0 (hit but not global (miss on this device.) i(bhi[2:0]) 0 (global winner. ) search3 (miss on this device.) |(lhi[6:0]) 0 bho[2:0] 0 a1 0 z 0 1 1 1 z z z z z z winner.) figure 10-23. timing diagram for globally winning device in block number 3
cynse7012 8 document #: 38-02040 rev. *e page 48 of 137 cycle clk2x cmdv cmd[1:0] dq ce_l oe_l cmd[10:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 cfg = 0000000000000000, hlat = 001, tlsz = 10, lram = 0, ldev = 0. note: |(bhi[2:0]) stands for the boolean ?or? of the entire bus bhi[2:0]. note: |(lhi[6:0]) stands for the boolean ?or? for the entire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: each bit in lho[1:0] is the same logical signal. phs_l sadr[23:0] ssf ssv ale_l search1 search2 search4 d1 d2 d3 d4 01 01 01 01 search1 search3 a b a b a b a b z z z z z z lho[1:0] 0 (miss on this device.) (miss on this device.) i(bhi[2:0]) 0 (miss on this device.) search3 (miss on this device.) |(lhi[6:0]) 0 bho[2:0] 0 z figure 10-24. timing diagram for devices below the winning device in block number 3 (except the last device [device 30])
cynse7012 8 document #: 38-02040 rev. *e page 49 of 137 the following is the sequence of operation for a single 72-bit search command (also refer to the ?command and command parameters,? on page 22). cycle a : the host asic drives the cmdv high and applies search command code (10) on cmd[1:0] signals. {cmd[10], cmd[5:3]} signals must be driven with the index to the gmr pair for use in this search operation. cmd[8:6] signals must be driven with the same bits that will be driven on sadr[23:21] by this device if it has a hit. dq[71:0] must be driven with the 7 2- bit data to be compared. the cmd[2] signal must be driven to a logic 0. cycle b : the host asic continues to drive the cmdv high and applies search command (10) on cmd[1:0]. cmd[5:2] must be driven by the index of the comparand register pair for storing the 144-bit word presented on the dq bus during cycles a and b. cmd[8:6] signals must be driven with the index of the ssr that will be used for storing the address of the matching entry and the hit flag (see page 16 for the description of ssr[0:7]). the dq[71:0] continues to carry the 72-bit data to be compared. note . for 72-bit searches, the host asic must supply the same 72-bit data on dq[71:0] during both cycles a and b and the even and odd pair of gmrs selected for the compare must be programmed with the same value. cycle clk2x cmdv cmd[1:0] dq ce_l oe_l cmd[10:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 c fg = 0000000000000000, hlat = 001, tlsz = 10, lram = 1, ldev = 1. n ote: |(bhi[2:0)] stands for the boolean ?or? of the entire bus bhi[2:0]. n ote: |(lhi[6:0]) stands for the boolean ?or? for the entire bus lhi[6:0]. n ote: each bit in bho[2:0] is the same logical signal. n ote: each bit in lho[1:0] is the same logical signal. phs_l sadr[23:0] ssf ssv ale_l search1 search2 search4 d1 d2 d3 d4 01 01 01 01 search1 search3 a b a b a b a b z 0 0 lho[1:0] 0 (hit on some device (global miss; this device default i(bhi[2:0]) 0 (hit on some device search3 (hit on some device |(lhi[6:0]) 0 bho[2:0] 0 z 0 0 0 z 1 z 1 above.) above.) above.) driver.) 0 0 z z 0 1 figure 10-25. timing diagram for device number 6 in block number 3 (device 30 in depth-cascaded table)
cynse7012 8 document #: 38-02040 rev. *e page 50 of 137 the logical 72-bit search operation is shown in figure 10-26 . the entire table (31 devices of 72-bit entries) is compared to a 72- bit word k (presented on the dq bus in both cycles a and b of the command) using the gmr and the local mask bits. the effective gmr is the 72-bit word specified by the identical value in both even and odd gmr pairs in each of the eight devices and selecte d by the gmr index in the command?s cycle a. the 72-bit word k (presented on the dq bus in both cycles a and b of the command) is also stored in both even and odd comparand register pairs in each of the eight devices and selected by the comparand registe r index in command?s cycle b. in the x72 configuration, the even comparand register can be subsequently used by the learn command only in the first non-full device. the word k (presented on the dq bus in both cycles a and b of the command) is compared with each entry in the table starting at location 0. the first matching entry?s location address l is the winning addr ess that is driven as part of the sram address on the sadr[23:0] lines (see ?sram addressing? on page 105). the global winning device will drive the bus in a specific cycle. on global miss cycles the device with lram = 1 and ldev = 1 will be the default driver for such missed cycles. the search command is a pipelined operation and executes a search at half the rate of the frequency of clk2x for 72-bit searche s in x72-configured tables. the latency of sadr, ce_l, ale_l, we_l, ssv, and ssf from the 72-bit search command cycle (two clk2x cycles) is shown in table 10-16 . for up to 31 devices in the table (tlsz = 10), search latency from command to sram access cycle is 6. in addition, ssv and ssf shift further to the right for different values of hlat, as specified in table 10-17 . table 10-16. the latency of search from instruction to sram access cycle number of devices max table size latency in clk cycles 1 (tlsz = 00) 64k 72 bits 4 1?8 (tlsz = 01) 512k 72 bits 5 1?31 (tlsz = 10) 1984k 72 bits 6 table 10-17. shift of ssf and ssv from sadr hlat number of clk cycles 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 cfg = 0000000000000000 71 0 location 0 1 2 3 2031615 (72-bit configuration) address k gmr comparand register (odd) comparand register (even) k k 71 0 71 0 (first matching entry) l must be same in each of the 31 devices will be same in each of the 31 devices figure 10-26. x72 table with 31 devices
cynse7012 8 document #: 38-02040 rev. *e page 51 of 137 10.6.4 144-bit search on tables configured as x144 using a single cynse70128 device figure 10-27 shows the timing diagram for a search command in the 144-bit-configured table (cfg = 0101010101010101) consisting of a single device for one set of parameters: tlsz = 00, hlat = 001, lram = 1, and ldev = 1. the hardware diagram for this search subsystem is shown in figure 10-28 . the following is the operation sequence for a single 144-bit search command (also refer to ?command and command param- eters,? on page 22). cycle a : the host asic drives the cmdv high and applies search command code (10) to cmd[1:0] signals. {cmd[10],cmd[5:3]} signals must be driven with the index to the gmr pair for use in this search operation. cmd[8:6] signals must be driven with the same bits that will be driven on sadr[23:21] by this device if it has a hit. dq[71:0] must be driven wi th the 72-bit data ([143:72]) to be compared against all even locations. the cmd[2] signal must be driven to logic 0. cycle clk2x cmdv cmd[1:0] ce_l oe_l hit hit miss miss cmd[10:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 cfg = 0101010101010101, hlat = 001, tlsz = 00, lram = 1, ldev = 1. phs_l sadr[23:0] ssf ssv ale_l search1 search2 search3 search4 a1 a3 01 01 01 01 search1 search3 a b a b a b a b 0 1 0 0 1 1 0 1 1 0 0 0 1 0 1 1 0 1 1 0 0 0 1 0 0 1 1 1 a b a b a b a b dq d1 d2 d3 d4 figure 10-27. timing diagram for 144-bit search (one device) lho[0] 6543210 lhi lho[1] bhi[2:0] dq[71:0] sram cynse70128 cmdv, cmd[10:0] bho[2:0] ssf, ssv figure 10-28. hardware diagram for a table with one device
cynse7012 8 document #: 38-02040 rev. *e page 52 of 137 cycle b : the host asic continues to drive the cmdv high and applies the command code of search command (10) on cmd[1:0]. cmd[5:2] must be driven by the index of the comparand register pair for storing the 144-bit word presented on the dq bus during cycles a and b. cmd[8:6] signals must be driven with the index of the ssr that will be used for storing the address of the matching entry and hit flag (see page 8 for the description of ssr[0:7]). the dq[71:0] is driven with 72-bit data ([71:0]), compared to all odd locations. note . for 144-bit searches, the host asic must supply two distinct 72-bit data words on dq[71:0] during cycles a and b. the even-numbered gmr of the pair specified by the gmr index is used for masking the word in cycle a. the odd-numbered gmr of the pair specified by the gmr index is used for masking the word in cycle b. the logical 144-bit search operation is shown in figure 10-29 . the entire table of 144-bit entries is compared to a 144-bit word k (presented on the dq bus in cycles a and b of the command) using the gmr and the local mask bits. the gmr is the 144-bit word specified by the even and odd global mask pair selected by the gmr index in the command?s cycle a. the 144-bit word k (presented on the dq bus in cycles a and b of the command) is also stored in both even and odd comparand register pairs selected by the comparand register index in the command?s cycle b. the two comparand registers can subsequently be used by the learn command with the even comparand register stored in an even location, and the odd comparand register stored in an adjacent odd location. the word k (presented on the dq bus in cycles a and b of the command) is compared with each entry in the table starting at location 0. the first matching entry?s location address l is the winning address that is driven as par t of the sram address on the sadr[23:0] lines (see ?sram addressing? on page 105). note . the matching address is always going to an even address for a 144-bit search. the search command is a pipelined operation that executes searches at half the rate of the frequency of clk2x for 144-bit searches in x144-configured tables. the latency of sadr, ce_l , ale_l, we_l, ssv, and ssf from the 144-bit search command cycle (two clk2x cycles) is shown in table 10-18 . for a single device in the table with tlsz = 00, the latency of the search from command to sram access cycle is 4. in addition, ssv and ssf shift further to the right for different values of hlat, as specified in table 10-19 . table 10-18. the latency of search from instruction to sram access cycle number of devices max table size latency in clk cycles 1 (tlsz = 00) 32k 144 bits 4 1?8 (tlsz = 01) 256k 144 bits 5 1?31 (tlsz = 10) 992k 144 bits 6 table 10-19. shift of ssf and ssv from sadr hlat number of clk cycles 000 0 001 1 010 2 011 3 cfg = 0101010101010101 143 0 location 0 2 4 6 32766 (144-bit configuration) address k gmr comparand register (odd) comparand register (even) a b 143 0 71 0 (first matching entry) l a b even odd figure 10-29. x144 table with one device
cynse7012 8 document #: 38-02040 rev. *e page 53 of 137 10.6.5 144-bit search on tables configured as x144 using up to eight cynse70128 devices the hardware diagram of the search subsystem of eight devices is shown in figure 10-30 . the following are parameters programmed into the eight devices. first seven devices (devices 0?6): cfg = 0101010101010101, tlsz = 01, hlat = 010, lram = 0, and ldev = 0. eighth device (device 7): cfg = 0101010101010101, tlsz = 01, hlat = 010, lram = 1, and ldev = 1. note . all eight devices must be programmed with the same value of tlsz and hlat. only the last device in the table must be programmed with lram = 1 and ldev = 1 (device number 7 in this case). all other upstream devices must be programmed with lram = 0 and ldev = 0 (devices 0 through 6 in this case). figure 10-31 shows the timing diagram for a search command in the 144-bit-configured table of eight devices for device 0. figure 10-32 shows the timing diagram for a search command in the 144-bit-configured table consisting of eight devices for device number 1. figure 10-33 shows the timing diagram for a search command in the 144-bit configured table consisting of eight devices for device number 7 (the last device in this specific table). for these timing diagrams, four 144-bit searches ar e performed sequentially, and the following hit/miss assumptions were made (see table 10-20 ). 100 4 101 5 110 6 111 7 table 10-20. hit/miss assumption search number1234 device 0 hit miss hit miss device 1 miss hit hit miss device 2?6 miss miss miss miss device 7 miss miss hit hit table 10-19. shift of ssf and ssv from sadr (continued) hlat number of clk cycles
cynse7012 8 document #: 38-02040 rev. *e page 54 of 137 lho[0] 6543210 lhi lho[0] 65 32 10 lhi lho[1] 6543 210 lhi lho[0] 654321 0 lhi lho[0] 654 3210 lhi lho[0] 65 4 3210 lhi lho[0] 654 32 10 lhi bho[0] 65 4 3210 lhi lho[0] lhi lhi lhi lho[1] lho[1] lho[1] bho[1] bho[0] bho[1] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] dq[71:0] sram lho[1] lho[0] cynse70128 #0 cynse70128 #1 cynse70128 #2 cynse70128 #3 cynse70128 #4 cynse70128 #5 cynse70128 #6 cynse70128 #7 4 bho[2] bho[2] cmdv cmd[10:0] ssf, ssv figure 10-30. hardware diagram for a table with eight devices
cynse7012 8 document #: 38-02040 rev. *e page 55 of 137 cycle clk2x cmdv cmd[1:0] ce_l oe_l (this cmd[10:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 c fg = 0101010101010101, hlat = 010, tlsz = 01, lram = 0, ldev = 0. n ote: |(lhi[6:0]) stands for the boolean ?or? of the entire bus lhi[6:0]. n ote: each bit in lho[1:0] is the same logical signal. phs_l sadr[23:0] ssf ssv ale_l search1 search2 search3 search4 01 01 01 01 search1 search3 a b a b a b a b a1 a3 z z z z z z z z z z z z z z z 0 0 1 0 0 1 1 1 1 1 z z z z device is the global winner.) (this device is the global winner.) |(lhi[6:0]) 0 (miss on this device.) (miss on this device.) lho[1:0] a b a b a b a b dq d1 d2 d3 d4 figure 10-31. timing diagram for 144-bit search device number 0
cynse7012 8 document #: 38-02040 rev. *e page 56 of 137 cycle clk2x cmdv cmd[1:0] ce_l oe_l (miss cmd[10:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 cfg = 0101010101010101, hlat = 010, tlsz = 01, lram = 0, ldev = 0. note: |(lhi[6:0]) stands for the boolean ?or? of the entire bus lhi[6:0]. note: each bit in lho[1:0] is the same logical signal. phs_l sadr[23:0] ssf ssv ale_l search1 search2 search3 search4 01 01 01 01 search1 search3 a b a b a b a b a2 z z z z 1 1 z z (local winner but not global winner.) (miss on this device.) lhi[6:0] lho[1:0] z 0 z z 0 z z 1 z on this device.) (this device global winner.) is a b a b a b a b dq d1 d2 d3 d4 figure 10-32. timing diagram for 144-bit search device number 1
cynse7012 8 document #: 38-02040 rev. *e page 57 of 137 the following is the sequence of operation for a single 144-bit search command (also see ?commands and command param- eters? on page 22). cycle a : the host asic drives cmdv high and applies search command code (10) on cmd[1:0] signals. {cmd[10],cmd[5:3]} signals must be driven with the index to the gmr pair for use in this search operation. cmd[8:6] signals must be driven with the same bits that will be driven by this device on sadr[23:21] if it has a hit. dq[71:0] must be driven with the 72-bit data ([143:72]) in order to be compared against all even locations. the cmd[2] signal must be driven to a logic 0. cycle b : the host asic continues to drive cmdv high and to apply the command code for search command (10) on cmd[1:0]. cmd[5:2] must be driven by the index of the comparand register pair for storing the 144-bit word presented on the dq bus during cycles a and b. cmd[8:6] signals must be driven with the ssr index that will be used for storing the address of the matching entry and the hit flag (see page 8 for the description of ssr[0:7]). the dq[71:0] is driven with 72-bit data ([71:0]) compared against all odd locations. the logical 144-bit search operation is shown in figure 10-34 . the entire table (eight devices of 144-bit entries) is compared to a 144-bit word k (presented on the dq bus in cycles a and b of the command) using the gmr and local mask bits. the gmr is the 144-bit word specified by the even and odd global mask pair selected by the gmr index in the command?s cycle a. cycle clk2x cmdv cmd[1:0] ce_l oe_l (miss on cmd[10:2] search2 search4 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 c fg = 0101010101010101, hlat = 010, tlsz = 01, lram = 1, ldev = 1. n ote: |(lhi[6:0]) stands for the boolean ?or? of the entire bus lhi[6:0]. n ote: each bit in lho[1:0] is the same logical signal. phs_l sadr[23:0] ssf ssv search1 search2 search3 search4 01 01 01 01 search1 search3 a b a b a b a b a4 0 (local but not global winner) (global winner.) |(lhi[6:0]) lho[1:0] this device) 0 z 0 0 z 0 ale_l we_l 1z 1 0 z 1 0 0 z 1 0 a b a b a b a b dq d1 d2 d3 d4 figure 10-33. timing diagram for 144-bit search device number 7 (last device) (miss on this device)
cynse7012 8 document #: 38-02040 rev. *e page 58 of 137 the 144-bit word k (presented on the dq bus in cycles a and b of the command) is also stored in the even and odd comparand registers specified by the comparand register index in the command?s cycle b. in x144 configurations, the even and odd comparand registers can subsequently be used by the learn command in only one of the devices (the first non-full device). the word k (presented on the dq bus in cycles a and b of the command) is compared to each entry in the table starting at location 0. the first matching entry?s location, address l, is the winning address that is driven as part of the sram address on the sadr[2 3:0] lines (see ?sram addressing? on page 105). the global winning device will drive the bus in a specific cycle. on global miss cycl es the device with lram = 1 (the default driving device for the sram bus) and ldev = 1 (the default driving device for ssf and ssv signals) will be the default driver for such missed cycles. note . during 144-bit searches of 144-bit-configured tables, the search hit will always be at an even address. the search command is a pipelined operation and executes a search at half the rate of the frequency of clk2x for 144-bit searches in x144-configured tables. the latency of sadr, ce_l , ale_l, we_l, ssv, and ssf from the 144-bit search command cycle (two clk2x cycles) is shown in table 10-21 . for one to eight devices in the table and tlsz = 01, the latency of a search from command to sram access cycle is 5. in addition , ssv and ssf shift further to the right for different values of hlat as specified in table 10-22 . table 10-21. search latency from instruction to sram access cycle number of devices max table size latency in clk cycles 1 (tlsz = 00) 32k 144 bits 4 1?8 (tlsz = 01) 256k 144 bits 5 1?31 (tlsz = 10) 992k 144 bits 6 table 10-22. shift of ssf and ssv from sadr hlat number of clk cycles 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 cfg = 0101010101010101 143 0 location 0 2 4 6 262142 (144-bit configuration) address k gmr comparand register (odd) comparand register (even) a b 143 0 71 0 (first matching entry) l a b even odd will be same in each of the eight devices must be same in each of the eight devices figure 10-34. x144 table with eight devices
cynse7012 8 document #: 38-02040 rev. *e page 59 of 137 10.6.6 144-bit search on tables configured as x144 using up to 31 cynse70128 devices the hardware diagram of the search su bsystem of 31 devices is shown in figure 10-35 . each of the four blocks in the diagram represents a block of eight cynse70128 devices (except the last, which has seven devices). the diagram for a block of eight devices is shown in figure 10-36 . following are the parameters programmed into the 31 devices. first thirty devices (devices 0?29): cfg = 0101010101010101, tlsz = 10, hlat = 001, lram = 0, and ldev = 0. thirty-first device (device 30): cfg = 0101010101010101, tlsz = 10, hlat = 001, lram = 1, and ldev = 1. note . all 31 devices must be programmed with the same value of tlsz and hlat. only the last device in the table must be programmed with lram = 1 and ldev = 1 (device number 30 in this case). all other upstream devices must be programmed with lram = 0 and ldev = 0 (devices 0 through 29 in this case). the timing diagrams referred to in this paragraph reference the hit/miss assumptions defined in table 10-23 . for the purpose of illustrating timings, it is further assumed that the there is only one device with a matching entry in each of the blocks. figure 10- 37 shows the timing diagram for a search command in the 144-bit-configured table (31 devices) for each of the eight devices in block number 0. figure 10-38 shows the timing diagram for search command in the 72-bit-configured table (31 devices) for all the devices in block number 1 above the winning device in that block. figure 10-39 shows the timing diagram for the globally winning device (the final winner within its own block and all blocks) in block number 1. figure 10-40 shows the timing diagram for all the devices below the globally winning device in block number 1. figure 10-41 , figure 10-42 , and figure 10-43 respectively show the timing diagrams of the devices above globally winning device, the globally winning device and devices below the global ly winning device for block number 2. figure 10-44 , figure 10-45 , figure 10-46 , and figure 10-47 respectively show the timing diagrams of the devices above the globally winning device, the globally winning device, and devices below the globally winning device except the last device (device 30), and the last device (device 30) for block number 3. the 144-bit search operation is pipelined and executes as follow s. four cycles from the search command, each of the devices knows the outcome internal to it for that operation. in the fifth cycle after the search command, the devices in a block (being less than or equal to eight devices resolving the winner within them using the lhi[6:0] and lho[1:0] signalling mechanism) arbitrate for a winner amongst them. in the sixth cycle after the search command, the blocks (of devices) resolve the winning block throu gh the bhi[2:0] and bho[2:0] signalling mechanism. the winning device in the winning block is the global winning device for a sear ch operation. table 10-23. hit/miss assumption search number 1 2 3 4 block 0 miss miss miss miss block 1 miss miss hit miss block 2 miss hit hit miss block 3 hit hit miss miss
cynse7012 8 document #: 38-02040 rev. *e page 60 of 137 bho[2] block of 8 cynse70128s block 0 (devices 0?7) bho[1] bho[0] bhi[2] bhi[1] bhi[0] bhi[2] block of 7 cynse70128s block 3 (devices 24?30) bhi[1] bhi[0] gnd bho[2] bho[1] bho[0] bhi[2] bhi[1] bhi[0] gnd bhi[2] bhi[1] bhi[0] gnd block of 8 cynse70128s block 1 (devices 8?15) block of 8 cynse70128s block 2 (devices 16?23) dq[71:0] sram bho[2] bho[2] bho[1] bho[1] bho[0] bho[0] cmd[10:0], cmdv ssf, ssv figure 10-35. hardware diagram for a table with 31 devices
cynse7012 8 document #: 38-02040 rev. *e page 61 of 137 lho[0] 6543210 lhi lho[0] 65 32 10 lhi lho[1] 6543 210 lhi lho[0] 654321 0 lhi lho[0] 654 3210 lhi lho[0] 65 4 3210 lhi lho[0] 654 32 10 lhi bho[0] 654 3210 lhi lho[0] lhi lhi lhi lho[1] lho[1] lho[1] bho[1] bho[0] bho[1] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] dq[71:0] sram lho[1] lho[0] cynse70128 #0 cynse70128 #1 cynse70128 #2 cynse70128 #3 cynse70128 #4 cynse70128 #5 cynse70128 #6 cynse70128 #7 4 bho[2] bho[2] cmdv cmd[10:0] bhi[2:0] ssv, ssf figure 10-36. hardware diagram for a block of up to eight devices
cynse7012 8 document #: 38-02040 rev. *e page 62 of 137 cycle clk2x cmdv cmd[1:0] dq ce_l oe_l cmd[10:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 c fg = 0101010101010101, hlat = 001, tlsz = 10, lram = 0, ldev = 0. n ote: |(bhi[2:0]) stands for the boolean ?or? of the entire bus bhi[2:0]. n ote: |(lhi[6:0]) stands for the boolean ?or? for the entire bus lhi[6:0]. n ote: each bit in bho[2:0] is the same logical signal. n ote: each bit in lho[1:0] is the same logical signal. phs_l sadr[23:0] ssf ssv ale_l search1 search2 search4 d1 d2 d3 d4 01 01 01 01 search1 search3 a b a b a b a b z z z z z z z lho[1:0] 0 (miss on this device.) (miss on this device.) i(bhi[2:0]) 0 (miss on this device.) search3 (miss on this device.) |(lhi[6:0]) 0 bho[2:0] 0 a b a b a b a b figure 10-37. timing diagram for each device in block number 0 (miss on each device)
cynse7012 8 document #: 38-02040 rev. *e page 63 of 137 cycle clk2x cmdv cmd[1:0] ce_l oe_l cmd[10:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 c fg = 0101010101010101, hlat = 001, tlsz = 10, lram = 0, ldev = 0. n ote: |(bhi[2:0]) stands for the boolean ?or? of the entire bus bhi[2:0]. n ote: |(lhi[6:0]) stands for the boolean ?or? for the entire bus lhi[6:0]. n ote: each bit in bho[2:0] is the same logical signal. n ote: each bit in lho[1:0] is the same logical signal. phs_l sadr[23:0] ssf ssv ale_l search1 search2 search4 01 01 01 01 search1 search3 a b a b a b a b z z z z z z z lho[1:0] 0 (miss on this device.) (miss on this device.) i(bhi[2:0]) 0 (miss on this device.) search3 (miss on this device.) |(lhi[6:0]) 0 bho[2:0] 0 a b a b a b a b dq d1 d2 d3 d4 figure 10-38. timing diagram for each device above the winning device in block number 1
cynse7012 8 document #: 38-02040 rev. *e page 64 of 137 cycle clk2x cmdv cmd[1:0] ce_l oe_l cmd[10:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 c fg = 0101010101010101, hlat = 001, tlsz = 10, lram = 0, ldev = 0. n ote: |(bhi[2:0]) stands for the boolean ?or? of the entire bus bhi[2:0]. n ote: |(lhi[6:0]) stands for the boolean ?or? for the entire bus lhi[6:0]. n ote: each bit in bho[2:0] is the same logical signal. n ote: each bit in lho[1:0] is the same logical signal. phs_l sadr[23:0] ssf ssv ale_l search1 search2 search4 01 01 01 01 search1 search3 a b a b a b a b z z z z z z z lho[1:0] 0 (miss on this device.) (miss on this device.) i(bhi[2:0]) 0 (miss on this device.) search3 (this device global winner.) |(lhi[6:0]) 0 bho[2:0] 0 a3 a b a b a b a b dq d1 d2 d3 d4 1zz 1z 1z 0 z 0 z z figure 10-39. timing diagram for globally winning device in block number 1
cynse7012 8 document #: 38-02040 rev. *e page 65 of 137 cycle clk2x cmdv cmd[1:0] ce_l oe_l cmd[10:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 c fg = 0101010101010101, hlat = 001, tlsz = 10, lram = 0, ldev = 0. n ote: |(bhi[2:0] stands for the boolean ?or? of the entire bus bhi[2:0]. n ote: |(lhi(6:0) stands for the boolean ?or? for the entire bus lhi[6:0]. n ote: each bit in bho[2:0] is the same logical signal. n ote: each bit in lho[1:0] is the same logical signal. phs_l sadr[23:0] ssf ssv ale_l search1 search2 search4 01 01 01 01 search1 search3 a b a b a b a b z z z z z z z lho[1:0] 0 (miss on this device.) (miss on this device.) i(bhi[2:0]) 0 (miss on this device.) search3 (miss on this device.) |(lhi[6:0]) 0 bho[2:0] 0 a b a b a b a b dq d1 d2 d3 d4 figure 10-40. timing diagram for devices below the winning device in block number 1
cynse7012 8 document #: 38-02040 rev. *e page 66 of 137 cycle clk2x cmdv cmd[1:0] ce_l oe_l cmd[10:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 c fg = 0101010101010101, hlat = 001, tlsz = 10, lram = 0, ldev = 0. n ote: |(bhi[2:0]) stands for the boolean ?or? of the entire bus bhi[2:0]. n ote: |(lhi[6:0]) stands for the boolean ?or? for the entire bus lhi[6:0]. n ote: each bit in bho[2:0] is the same logical signal. n ote: each bit in lho[1:0] is the same logical signal. phs_l sadr[23:0] ssf ssv ale_l search1 search2 search4 01 01 01 01 search1 search3 a b a b a b a b z z z z z z z lho[1:0] 0 (miss on this device.) (miss on this device.) i(bhi[2:0]) 0 (miss on this device.) search3 (miss on this device.) |(lhi[6:0]) 0 bho[2:0] 0 a b a b a b a b dq d1 d2 d3 d4 figure 10-41. timing diagram for devices above the winning device in block number 2
cynse7012 8 document #: 38-02040 rev. *e page 67 of 137 cycle clk2x cmdv cmd[1:0] ce_l oe_l cmd[10:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 c fg = 0101010101010101, hlat = 001, tlsz = 10, lram = 0, ldev = 0. n ote: |(bhi[2:0]) stands for the boolean ?or? of the entire bus bhi[2:0]. n ote: |(lhi[6:0]) stands for the boolean ?or? for the entire bus lhi[6:0]. n ote: each bit in bho[2:0] is the same logical signal. n ote: each bit in lho[1:0] is the same logical signal. phs_l sadr[23:0] ssf ssv ale_l search1 search2 search4 01 01 01 01 search1 search3 a b a b a b a b z z z z z z lho[1:0] 0 (global winner.) (miss on this device.) i(bhi[2:0]) 0 (miss on this device.) search3 (hit but not winner.) |(lhi[6:0]) 0 bho[2:0] 0 a2 0 z 0 1 1 1 z z z z z z a b a b a b a b dq d1 d2 d3 d4 figure 10-42. timing diagram for globally winning device in block number 2
cynse7012 8 document #: 38-02040 rev. *e page 68 of 137 cycle clk2x cmdv cmd[1:0] ce_l oe_l cmd[10:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 c fg = 0101010101010101, hlat = 001, tlsz = 10, lram = 0, ldev = 0. n ote: |(bhi[2:0]) stands for the boolean ?or? of the entire bus bhi[2:0]. n ote: |(lhi[6:0]) stands for the boolean ?or? for the entire bus lhi[6:0]. n ote: each bit in bho[2:0] is the same logical signal. n ote: each bit in lho[1:0] is the same logical signal. phs_l sadr[23:0] ssf ssv ale_l search1 search2 search4 01 01 01 01 search1 search3 a b a b a b a b z z z z z z lho[1:0] 0 (miss on this device.) (miss on this device.) i(bhi[2:0]) 0 (miss on this device.) search3 (miss on this device.) |(lhi[6:0]) 0 bho[2:0] 0 z a b a b a b a b dq d1 d2 d3 d4 figure 10-43. timing diagram for devices below the winning device in block number 2
cynse7012 8 document #: 38-02040 rev. *e page 69 of 137 cycle clk2x cmdv cmd[1:0] ce_l oe_l cmd[10:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 c fg = 0101010101010101, hlat = 001, tlsz = 10, lram = 0, ldev = 0. n ote: |(bhi[2:0]) stands for the boolean ?or? of the entire bus bhi[2:0]. n ote: |(lhi[6:0]) stands for the boolean ?or? for the entire bus lhi[6:0]. n ote: each bit in bho[2:0] is the same logical signal. n ote: each bit in lho[1:0] is the same logical signal. phs_l sadr[23:0] ssf ssv ale_l search1 search2 search4 01 01 01 01 search1 search3 a b a b a b a b z z z z z z lho[1:0] 0 (miss on this device.) (miss on this device.) i(bhi[2:0]) 0 (miss on this device.) search3 (miss on this device.) |(lhi[6:0]) 0 bho[2:0] 0 z a b a b a b a b dq d1 d2 d3 d4 figure 10-44. timing diagram for devices above the winning device in block number 3
cynse7012 8 document #: 38-02040 rev. *e page 70 of 137 cycle clk2x cmdv cmd[1:0] ce_l oe_l cmd[10:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 c fg = 0101010101010101, hlat = 001, tlsz = 10, lram = 0, ldev = 0. n ote: |(bhi[2:0]) stands for the boolean ?or? of the entire bus bhi[2:0]. n ote: |(lhi[6:0]) stands for the boolean ?or? for the entire bus lhi[6:0]. n ote: each bit in bho[2:0] is the same logical signal. n ote: each bit in lho[1:0] is the same logical signal. phs_l sadr[23:0] ssf ssv ale_l search1 search2 search4 01 01 01 01 search1 search3 a b a b a b a b z z z z z z lho[1:0] 0 (hit but not global (miss on this device.) i(bhi[2:0]) 0 (global winner.) search3 (miss on this device.) |(lhi[6:0]) 0 bho[2:0] 0 a1 0 z 0 1 1 1 z z z z z z winner.) a b a b a b a b dq d1 d2 d3 d4 figure 10-45. timing diagram for globally winning device in block number 3
cynse7012 8 document #: 38-02040 rev. *e page 71 of 137 cycle clk2x cmdv cmd[1:0] ce_l oe_l cmd[10:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 c fg = 0101010101010101, hlat = 001, tlsz = 10, lram = 0, ldev = 0. n ote: |(bhi[2:0]) stands for the boolean ?or? of the entire bus bhi[2:0]. n ote: |(lhi[6:0]) stands for the boolean ?or? for the entire bus lhi[6:0]. n ote: each bit in bho[2:0] is the same logical signal. n ote: each bit in lho[1:0] is the same logical signal. phs_l sadr[23:0] ssf ssv ale_l search1 search2 search4 01 01 01 01 search1 search3 a b a b a b a b z z z z z z lho[1:0] 0 (miss on this device.) (miss on this device.) i(bhi[2:0]) 0 (miss on this device.) search3 (miss on this device.) |(lhi[6:0]) 0 bho[2:0] 0 z a b a b a b a b dq d1 d2 d3 d4 figure 10-46. timing diagram for devices below the winning device in block number 3 except device 30 (the last device)
cynse7012 8 document #: 38-02040 rev. *e page 72 of 137 the following is the sequence of operation for a single 144-bit search command (also refer to ?command and command parameters,? on page 22). cycle a : the host asic drives the cmdv high and applies search command code (10) on cmd[1:0] signals. {cmd[10], cmd[5:3]} signals must be driven with the index to the gmr pair for use in this search operation. cmd[8:6] signals must be driven with the bits that will be driven on sadr[23:21] by this device if it has a hit. dq[71:0] must be driven with the 72-bit data ([143:72]) in order to be compared against all even locations. the cmd[2] signal must be driven to logic 0. cycle clk2x cmdv cmd[1:0] ce_l oe_l cmd[10:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 c fg = 0101010101010101, hlat = 001, tlsz = 10, lram = 1, ldev = 1. n ote: |(bhi[2:0)] stands for the boolean ?or? of the entire bus bhi[2:0]. n ote: |(lhi[6:0]) stands for the boolean ?or? for the entire bus lhi[6:0]. n ote: each bit in bho[2:0] is the same logical signal. n ote: each bit in lho[1:0] is the same logical signal. phs_l sadr[23:0] ssf ssv ale_l search1 search2 search4 01 01 01 01 search1 search3 a b a b a b a b z 0 0 lho[1:0] 0 (hit on some device (global miss; this device default i(bhi[2:0]) 0 (hit on some device search3 (hit on some device |(lhi[6:0]) 0 bho[2:0] 0 z 0 0 0 z 1 z 1 above.) above.) above.) driver.) 0 0 z z 0 1 a b a b a b a b dq d1 d2 d3 d4 figure 10-47. timing diagram for device number 6 in block number 3 (device 30 in depth-cascaded table)
cynse7012 8 document #: 38-02040 rev. *e page 73 of 137 cycle b : the host asic continues to drive the cmdv high and to apply search command code (10) on cmd[1:0]. cmd[5:2] must be driven by the index of the comparand register pair for storing the 144-bit word presented on the dq bus during cycles a and b. cmd[8:6] signals must be driven with the index of the ssr that will be used for storing the address of the matching entry and the hit flag (see page 16 for the description of ssr[0:7]). the dq[71:0] is driven with 72-bit data ([71:0])to be com pared against all odd locations. the logical 144-bit search operation is as shown in figure 10-48 . the entire table of 31 devices (consisting of 144-bit entries) is compared against a 144-bit word k that is presented on the dq bus in cycles a and b of the command using the gmr and local mask bits. the gmr is the 144-bit word specified by the even and odd global mask pair selected by the gmr index in the command?s cycle a. the 144-bit word k that is presented on the dq bus in cycles a and b of the command is also stored in the even and odd comparand registers specified by the comparand register index in the command?s cycle b. in x144 configurations, the even and odd comparand registers can subsequently be used by the learn command in only the first non-full device. note . the learn command is supported for only one of the blocks consisting of up to eight devices in a depth-cascaded table of more than one block. the word k that is presented on the dq bus in cycles a and b of the command is compared with each entry in the table starting at location 0. the first matching entry?s location address l is the winning address that is driven as part of the sram address on the sadr[23:0] lines (see ?sram addressing? on page 1 05). the global winning device will drive the bus in a specific cycle. on global miss cycles the device with lram = 1 (the default driving device for the sram bus) and ldev = 1 (the default driving device for ssf and ssv signals) will be the default driver for such missed cycles. note . during 144-bit searches of 144- bit-configured tables, the search hit will always be at an even address. the search command is a pipelined operation. it executes a search at half the rate of the frequency of clk2x for 144-bit search es in x144-configured tables. the latency of sadr, ce_l, ale_l, we_l, ssv, and ssf from the 144-bit search command cycle (two clk2x cycles) is shown in table 10-24 . the latency of a search from command to the sram access cycle is 6 for 1?31 devices in the table and where tlsz = 10. in addition, ssv and ssf shift further to the right for different values of hlat, as specified in table 10-25 . table 10-24. the latency of search from instruction to sram access cycle number of devices max table size latency in clk cycles 1 (tlsz = 00) 32k 144 bits 4 1?8 (tlsz = 01) 256k 144 bits 5 1?31 (tlsz = 10) 992k 144 bits 6 table 10-25. shift of ssf and ssv from sadr hlat number of clk cycles 000 0 001 1 010 2 011 3 cfg = 0101010101010101 143 0 location 0 2 4 6 1015806 (144-bit configuration) address k gmr comparand register (odd) comparand register (even) a b 143 0 71 0 (first matching entry) l a b even odd will be same in each of the 31 devices must be same in each of the 31 devices figure 10-48. x144 table with 31 devices
cynse7012 8 document #: 38-02040 rev. *e page 74 of 137 10.6.7 288-bit search on tables configured as x288 using a single cynse70128 device figure 10-49 shows the timing diagram for a search command in the 288-bit-configured table (cfg = 1010101010101010) consisting of a single device for one set of parameters: tlsz = 00, hlat = 001, lram = 1, and ldev = 1. the hardware diagram for this search subsystem is shown in figure 10-50 . 100 4 101 5 110 6 111 7 table 10-25. shift of ssf and ssv from sadr (continued) hlat number of clk cycles cycle clk2x cmdv cmd[1:0] ce_l oe_l hit miss cmd[10:2] we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 c fg = 1010101010101010, hlat = 001, tlsz = 00, lram = 1, ldev = 1. phs_l sadr[23:0] ssf ssv ale_l search1 search2 a1 01 01 search1 search2 a b a b a b a b 0 1 0 0 1 1 0 0 1 1 0 1 0 0 a b c d a b c d dq d1 d2 cmd[2] 1 0 1 10 1 figure 10-49. timing diagram for 288-bit search (one device)
cynse7012 8 document #: 38-02040 rev. *e page 75 of 137 the following is the sequence of operation for a single 144-bit search command (also refer to ?commands and command parameters? on page 22). cycle a : the host asic drives the cmdv high and applies search command code (10) on cmd[1:0] signals. {cmd[10], cmd[5:3]} signals must be driven with the index to the gmr pair used for bits [287:144] of the data being searched. dq[71:0] must be driven with the 72-bit data ([287:216]) to be compared to all locations 0 in the four 72-bits-word page. the cmd[2] signal must be driven to logic 1. note . cmd[2] = 1 signals that the search is a x288-bit search. cmd[8:3] in this cycle is ignored. cycle b : the host asic continues to drive the cmdv high and continues to apply the command code of search command (10) on cmd[1:0]. the dq[71:0] is driven with the 72-bit data ([2 15:144]) to be compared to all locations 1 in the four 72-bits- word page. cycle c : the host asic drives the cmdv high and applies search command code (10) on cmd[1:0] signals. {cmd[10],cmd[5:3]} signals must be driven with the index to the gmr pair used for bits [143:0] of the data being searched. cmd[8:6] signals must be driven with the bits that will be driven on sadr[23:21] by this device if it has a hit. dq[71:0] must be driven with the 72-bit data ([143:72]) to be compared to all locations 2 in the four 72-bits-word page. the cmd[2] signal must be driven to logic 0. cycle d : the host asic continues to drive the cmdv high and applies search command code (10) on cmd[1:0]. cmd[8:6] signals must be driven with the index of the ssr that will be used for storing the address of the matching entry and the hit fl ag (see page 8 for the description of ssr[0:7]). the dq[71:0] is driven with the 72-bit data ([71:0]) to be compared to all locati ons 3 in the four 72-bits-word page. cmd[5:2] is ignored because the learn instruction is not supported for x288 tables. note . for 288-bit searches, the host asic must supply four distinct 72-bit data words on dq[71:0] during cycles a, b, c, and d. the gmr index in cycle a selects a pair of gmrs that apply to dq data in cycles a and b. the gmr index in cycle c selects a pair of gmrs that apply to dq data in cycles c and d. the logical 288-bit search operation is shown in figure 10-51 . the entire table of 288-bit entries is compared to a 288-bit word k that is presented on the dq bus in cycles a, b, c, and d of the command using the gmr and local mask bits. the gmr is the 288-bit word specified by the two pairs of gmrs selected by the gmr indexes in the command?s cycles a and c. the 288-bit word k that is presented on the dq bus in cycles a, b, c and d of the command is compared with each entry in the table starting at location 0. the first matching entry?s location address l is the winning address that is driven as part of the sram address on sadr[23:0] lines (see ?sram addressing? on page 105). note . the matching address is always going to be location 0 in a four- entry page for a 288-bit search (two lsbs of the matching index will be 00). lho[0] 6543210 lhi lho[1] bhi[2:0] dq[71:0] sram cynse70128 cmdv, cmd[10:0] bho[2:0] ssf, ssv figure 10-50. hardware diagram for a table with one device cfg = 1010101010101010 287 0 location 0 4 8 12 16380 address k gmr 287 0 (first matching entry) l a b 01 c d 23 287 0 location 0 4 8 12 16380 (288-bit configuration) address k gmr 287 0 (first matching entry) l a b 01 c d 23 figure 10-51. x288 table with one device
cynse7012 8 document #: 38-02040 rev. *e page 76 of 137 the search command is a pipelined operation and executes at one-fourth the rate of the frequency of clk2x for 288-bit searches in x288-configured tables. the latency of sadr, ce_l, ale_l, we_l, ssv, and ssf from the 288-bit search command (measured in clk cycles) from the clk2x cycle that contains the c and d cycles is shown in table 10-26 . the latency of a search from command to sram access cycle is 4 for only a single device in the table and tlsz = 00. in addition , ssv and ssf shift further to the right for different values of hlat, as specified in table 10-27 . 10.6.8 288-bit search on tables configured as x288 using up to eight cynse70128 devices the hardware diagram of the search subsystem of eight devices is shown in figure 10-52 . the following are the parameters programmed in the eight devices. first seven devices (devices 0?6): cfg = 1010101010101010, tlsz = 01, hlat = 000, lram = 0, and ldev = 0. eighth device (device 7): cfg = 1010101010101010, tlsz = 01, hlat = 000, lram = 1, and ldev = 1. note . all eight devices must be programmed with the same value of tlsz and hlat. only the last device in the table must be programmed with lram = 1 and ldev = 1 (device number 7 in this case). all other upstream devices must be programmed with lram = 0 and ldev = 0 (devices 0 through 6 in this case). figure 10-53 shows the timing diagram for a search command in the 288-bit-configured table of eight devices for device number 0. figure 10-54 shows the timing diagram for a search command in the 288-bit-configured table of eight devices for device number 1. figure 10-55 shows the timing diagram for a search command in the 288-bit-configured table of eight devices for device number 7 (the last device in this specific table). for these timing diagrams three 288-bit searches are performed sequentially. the following hit/miss assumptions were made as shown in table 10-28 . table 10-26. the latency of search from cycles c and d to sram access cycle number of devices max table size latency in clk cycles 1 (tlsz = 00) 16k 288 bits 4 1?8 (tlsz = 01) 128k 288 bits 5 1?31 (tlsz = 10) 496k 288 bits 6 table 10-27. shift of ssf and ssv from sadr hlat number of clk cycles 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 table 10-28. hit/miss assumption search number 1 2 3 device 0 hit miss miss device 1 miss hit miss device 2?6 miss miss miss device 7 miss miss miss
cynse7012 8 document #: 38-02040 rev. *e page 77 of 137 lho[0] 6543210 lhi lho[0] 65 32 10 lhi lho[1] 6543 210 lhi lho[0] 654321 0 lhi lho[0] 654 3210 lhi lho[0] 65 4 3210 lhi lho[0] 654 32 10 lhi bho[0] 65 4 3210 lhi lho[0] lhi lhi lhi lho[1] lho[1] lho[1] bho[1] bho[0] bho[1] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] dq[71:0] sram lho[1] lho[0] cynse70128 #0 cynse70128 #1 cynse70128 #2 cynse70128 #3 cynse70128 #4 cynse70128 #5 cynse70128 #6 cynse70128 #7 4 bho[2] bho[2] cmdv cmd[10:0] ssf, ssv figure 10-52. hardware diagram for a table with eight devices
cynse7012 8 document #: 38-02040 rev. *e page 78 of 137 cycle clk2x cmdv ce_l oe_l (this we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 c fg = 1010101010101010, hlat = 000, tlsz = 01, lram = 0, ldev = 0. n ote: |(lhi[6:0]) stands for the boolean ?or? of the entire bus lhi[6:0]. n ote: each bit in lho[1:0] is the same logical signal. phs_l sadr[23:0] ale_l search1 search2 search3 a1 z z z z z z z 0 device is the global winner.) |(lhi[6:0]) 0 (miss on this device.) (miss on this device.) lho[1:0] cmd[1:0] cmd[10:2] 01 01 search1 search2 a b a b a b a b cmd[2] a b c d a b c d dq d1 d2 a b c d d3 a b a b 01 search3 z z 0 1 ssv z z 1 ssf z 1 z figure 10-53. timing diagram for 288-bit search device number 0
cynse7012 8 document #: 38-02040 rev. *e page 79 of 137 cycle clk2x ce_l oe_l (miss we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 c fg = 1010101010101010, hlat = 000, tlsz = 01, lram = 0, ldev = 0. n ote: |(lhi[6:0]) stands for the boolean ?or? of the entire bus lhi[6:0]. n ote: each bit in lho[1:0] is the same logical signal. phs_l sadr[23:0] ssf ssv ale_l search1 search2 a2 z z z z 1 1 z z |(lhi[6:0]) lho[1:0] z 0 z 1 z on this device.) (this device is global winner.) cmdv cmd[1:0] cmd[10:2] 01 01 search1 search2 a b a b a b a b cmd[2] a b c d a b c d dq d1 d2 a b c d d3 a b a b 01 search3 z z 0 (miss search3 on this device.) figure 10-54. timing diagram for 288-bit search device number 1
cynse7012 8 document #: 38-02040 rev. *e page 80 of 137 the following is the sequence of operation for a single 288-bit search command (also see ?commands and command param- eters? on page 22). cycle a : the host asic drives the cmdv high and applies search command code (10) on cmd[1:0] signals. {cmd[10], cmd[5:3]} signals must be driven with the index to the gmr pair used for bits [287:144] of the data being searched in this operation. dq[71:0] must be driven with the 72-bit data ([287:216]) to be compared against all locations 0 in the four-word 72- bit page. the cmd[2] signal must be driven to logic 1. note . cmd[2] = 1 signals that the search is a 288-bit search. cmd[8:3] in this cycle is ignored. cycle b : the host asic continues to drive the cmdv high and applies search command code (10) on cmd[1:0]. the dq[71:0] is driven with the 72-bit data ([215:144]) to be compared against all locations 1 in the four 72-bits-word page. cycle c : the host asic drives the cmdv high and applies search command code (10) on cmd[1:0] signals. {cmd[10], cmd[5:3]} signals must be driven with the index to the gmr pair used for bits [143:0] of the data being searched. cmd[8:6] signals must be driven with the bits that will be driven on sadr[23:21] by this device if it has a hit. dq[71:0] must be driven cycle clk2x cmdv ce_l oe_l (miss 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 c fg = 1010101010101010, hlat = 000, tlsz = 01, lram = 1, ldev = 1. n ote: |(lhi[6:0]) stands for the boolean ?or? of the entire bus lhi[6:0]. n ote: each bit in lho[1:0] is the same logical signal. phs_l sadr[23:0] ssf ssv search1 search2 search3 0 (global miss.) |(lhi[6:0]) lho[1:0] on this device.) (miss on this device.) 0 z 0 ale_l we_l 1z 1 0 z 1 0 0 z 0 cmd[1:0] cmd[10:2] 01 01 search1 search2 a b a b a b a b cmd[2] a b c d a b c d dq d1 d2 a b c d d3 a b a b 01 search3 z 0 0 z z 1 z z 0 0 z 0 figure 10-55. timing diagram for 288-bit search device number 7 (last device)
cynse7012 8 document #: 38-02040 rev. *e page 81 of 137 with the 72-bit data ([143:72]) to be compared against all locations 2 in the four 72-bits-word page. the cmd[2] signal must be driven to logic 0. cycle d : the host asic continues to drive the cmdv high and applies search command code (10) on cmd[1:0]. cmd[8:6] signals must be driven with the index of the ssr that will be used for storing the address of the matching entry and the hit fl ag (see page 16 for the description of ssr[0:7]). the dq[71:0] is driven with the 72-bit data ([71:0]) to be compared to all locat ions 3 in the four 72-bits-word page. cmd[5:2] is ignored because the learn instruction is not supported for x288 tables. note . for 288-bit searches, the host asic must supply four distinct 72-bit data words on dq[71:0] during cycles a, b, c, and d. the gmr index in cycle a selects a pair of gmrs in each of the eight devices that apply to dq data in cycles a and b. the gmr index in cycle c selects a pair of gmrs in each of the eight devices that apply to dq data in cycles c and d. the logical 288-bit search operation is shown in figure 10-56 . the entire table of 288-bit entries is compared to a 288-bit word k that is presented on the dq bus in cycles a, b, c, and d of the command using the gmr and the local mask bits. the gmr is the 288-bit word specified by the two pairs of gmrs selected by the gmr indexes in the command?s cycles a and c in each of the eight devices. the 288-bit word k that is presented on the dq bus in cycles a, b, c, and d of the command is compared to each entry in the table starting at location 0. the first matching entry?s location address l is the winning address that is dr iven as part of the sram address on the sadr[23:0] lines (see ?sram addressing? on page 105). note . the matching address is always going to be a location 0 in a four-entry page for 288-bit search (two lsbs of the matching index will be 00). the search command is a pipelined operation and executes search at one-fourth the rate of the frequency of clk2x for 288-bit searches in x288-configured tables. the latency of sadr, ce_l , ale_l, we_l, ssv, and ssf from the 288-bit search command (measured in clk cycles) from the clk2x cycle that contains the c and d cycles is shown in table 10-29 . the latency of search from command to sram access cycle is 5 for only a single device in the table and tlsz = 01. in addition, ssv and ssf shift further to the right for different values of hlat, as specified in table 10-30 . table 10-29. the latency of search from cycles c and d to sram access cycle number of devices max table size latency in clk cycles 1 (tlsz = 00) 16k 288 bits 4 1?8 (tlsz = 01) 128k 288 bits 5 1?31 (tlsz = 10) 496k 288 bits 6 table 10-30. shift of ssf and ssv from sadr hlat number of clk cycles 000 0 001 1 010 2 011 3 100 4 cfg = 1010101010101010 287 0 location 0 4 8 12 131068 (288-bit configuration) address k gmr 287 0 (first matching entry) l a b 01 c d 23 must be same in each of the eight devices figure 10-56. x288 table with eight devices
cynse7012 8 document #: 38-02040 rev. *e page 82 of 137 10.6.9 288-bit search on tables configured as x288 using up to 31 cynse70128 devices the hardware diagram of the search su bsystem of 31 devices is shown in figure 10-57 . each of the four blocks in the diagram represents a block of eight cynse70128 devices, except the last which has seven devices. the diagram for a block of eight devices is shown in figure 10-58 . the following are the parameters programmed into the 31 devices. first thirty devices (devices 0?29): cfg = 1010101010101010, tlsz = 10, hlat = 000, lram = 0, and ldev = 0. thirty-first device (device 30): cfg = 1010101010101010, tlsz = 10, hlat = 000, lram = 1, and ldev = 1. note . all 31 devices must be programmed with the same value of tlsz and hlat. only the last device in the table must be programmed with lram = 1 and ldev = 1 (device number 30 in this case). all other upstream devices must be programmed with lram = 0 and ldev = 0 (devices 0 through 29 in this case). the timing diagrams referred to in this paragraph reference the hit/miss assumptions defined in table 10-31 . for the purpose of illustrating the timings, it is further assumed that there is only one device with the matching entry in each block. figure 10-59 shows the timing diagram for a search command in the 288-bit-configured table consisting of 31 devices for each of the eight devices in block number 0. figure 10-60 shows the timing diagram for a search command in the 288-bit-configured table of 31 devices for all devices above the winning device in block number 1. figure 10-61 shows the timing diagram for the globally winning device (the final winner within its own and all blocks) in block number 1. figure 10-62 shows the timing diagram for all the devices below the globally winning device in block number 1. figure 10-63 , figure 10-64 , and figure 10-65 , respectively, show the timing diagrams of the devices above the globally winning device, the globally winning device, and the devices below the globally winn ing device for block number 2. figure 10-66 , figure 10-67 , figure 10-68 , and figure 10-69 , respectively, show the timing diagrams of the device above the globally winning device, the globally winning device, the devices below the globally winning device (ex cept device 30), and last device (device 30) for block number 3. the 288-bit search operation is pipelined and executes as follow s. four cycles from the last cycle of the search command each of the devices knows the outcome internal to it for that operation. in the fifth cycle from the search command, the devices in a block (which is less than or equal to eight devices resolving the winner within them using an lhi[6:0] and lho[1:0] signalling mechanism) arbitrate for a winner. in the sixth cycle after the search command, the blocks of devices resolve the winning block through a bhi[2:0] and bho[2:0] signalling mechanism. the winning device within the winning block is the global winning device for the search operation. 101 5 110 6 111 7 table 10-31. hit/miss assumption search number 1 2 3 block 0 missmissmiss block 1 miss miss hit block 2 miss hit hit block 3 hit hit miss table 10-30. shift of ssf and ssv from sadr hlat number of clk cycles
cynse7012 8 document #: 38-02040 rev. *e page 83 of 137 bho[2] block of 8 cynse70128s block 0 (devices 0?7) bho[1] bho[0] bhi[2] bhi[1] bhi[0] bhi[2] block of 7 cynse70128s block 3 (devices 24?30) bhi[1] bhi[0] gnd bho[2] bho[1] bho[0] bhi[2] bhi[1] bhi[0] gnd bhi[2] bhi[1] bhi[0] gnd block of 8 cynse70128s block 1 (devices 8?15) block of 8 cynse70128s block 2 (devices 16?23) dq[71:0] sram bho[2] bho[2] bho[1] bho[1] bho[0] bho[0] cmd[10:0], cmdv ssf, ssv figure 10-57. hardware diagram for a table with 31 devices
cynse7012 8 document #: 38-02040 rev. *e page 84 of 137 lho[0] 6543210 lhi lho[0] 65 32 10 lhi lho[1] 6543 210 lhi lho[0] 654321 0 lhi lho[0] 654 3210 lhi lho[0] 65 4 3210 lhi lho[0] 654 32 10 lhi bho[0] 654 3210 lhi lho[0] lhi lhi lhi lho[1] lho[1] lho[1] bho[1] bho[0] bho[1] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] dq[71:0] sram lho[1] lho[0] cynse70128 #0 cynse70128 #1 cynse70128 #2 cynse70128 #3 cynse70128 #4 cynse70128 #5 cynse70128 #6 cynse70128 #7 4 bho[2] bho[2] cmdv cmd[10:0] bhi[2:0] ssv, ssf figure 10-58. hardware diagram for a block of up to eight devices
cynse7012 8 document #: 38-02040 rev. *e page 85 of 137 cycle clk2x ce_l oe_l we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 c fg = 1010101010101010, hlat = 000, tlsz = 10, lram = 0, ldev = 0. n ote: |(bhi[2:0]) stands for the boolean ?or? of the entire bus bhi[2:0]. n ote: |(lhi[6:0]) stands for the boolean ?or? for the entire bus lhi[6:0]. n ote: each bit in bho[2:0] is the same logical signal. n ote: each bit in lho[1:0] is the same logical signal. phs_l sadr[23:0] ssf ssv ale_l search1 search2 z z z z z z z lho[1:0] 0 (miss on this device.) i(bhi[2:0]) 0 (misson this device.) search3 (misson this device) |(lhi[6:0]) 0 bho[2:0] 0 cmdv cmd[1:0] cmd[10:2] 01 01 search1 search2 a b a b a b a b cmd[2] a b c d a b c d dq d1 d2 a b c d d3 a b a b 01 search3 figure 10-59. timing diagram for each device in block number 0 (miss on each device)
cynse7012 8 document #: 38-02040 rev. *e page 86 of 137 cycle clk2x ce_l oe_l we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 c fg = 1010101010101010, hlat = 000, tlsz = 10, lram = 0, ldev = 0. n ote: |(bhi[2:0]) stands for the boolean ?or? of the entire bus bhi[2:0]. n ote: |(lhi[6:0]) stands for the boolean ?or? for the entire bus lhi[6:0]. n ote: each bit in bho[2:0] is the same logical signal. n ote: each bit in lho[1:0] is the same logical signal. phs_l sadr[23:0] ssf ssv ale_l search1 search2 z z z z z z z lho[1:0] 0 i(bhi[2:0]) 0 (miss on search3 |(lhi[6:0]) 0 bho[2:0] 0 cmdv cmd[1:0] cmd[10:2] 01 01 search1 search2 a b a b a b a b cmd[2] a b c d a b c d dq d1 d2 a b c d d3 a b a b 01 search3 this device.) (miss on this device.) (miss on this device.) figure 10-60. timing diagram for each device above the winning device in block number 1
cynse7012 8 document #: 38-02040 rev. *e page 87 of 137 cycle clk2x ce_l oe_l we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 c fg = 1010101010101010, hlat = 000, tlsz = 10, lram = 0, ldev = 0. n ote: |(bhi[2:0]) stands for the boolean ?or? of the entire bus bhi[2:0]. n ote: |(lhi[6:0]) stands for the boolean ?or? for the entire bus lhi[6:0]. n ote: each bit in bho[2:0] is the same logical signal. n ote: each bit in lho[1:0] is the same logical signal. phs_l sadr[23:0] ssf ssv ale_l search1 search2 z z z z z z z lho[1:0] 0 i(bhi[2:0]) 0 search3 (this device global winner.) |(lhi[6:0]) 0 bho[2:0] 0 a3 cmdv cmd[1:0] cmd[10:2] 01 01 search1 search2 a b a b a b a b cmd[2] a b c d a b c d dq d1 d2 a b c d d3 a b a b 01 search3 0 0 1 1 1 (miss on this device.) (miss on this device.) figure 10-61. timing diagram for globally winning device in block number 1
cynse7012 8 document #: 38-02040 rev. *e page 88 of 137 cycle clk2x ce_l oe_l we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 c fg = 1010101010101010, hlat = 000, tlsz = 10, lram = 0, ldev = 0. n ote: |(bhi[2:0]) stands for the boolean ?or? of the entire bus bhi[2:0]. n ote: |(lhi[6:0]) stands for the boolean ?or? for the entire bus lhi[6:0]. n ote: each bit in bho[2:0] is the same logical signal. n ote: each bit in lho[1:0] is the same logical signal. phs_l sadr[23:0] ssf ssv ale_l search1 search2 z z z z z z z lho[1:0] 0 (miss on this device.) i(bhi[2:0]) 0 (miss on this device.) search3 (miss on this device.) |(lhi[6:0]) 0 bho[2:0] cmdv cmd[1:0] cmd[10:2] 01 01 search1 search2 a b a b a b a b cmd[2] a b c d a b c d dq d1 d2 a b c d d3 a b a b 01 search3 0 figure 10-62. timing diagram for devices below the winning device in block number 1
cynse7012 8 document #: 38-02040 rev. *e page 89 of 137 cycle clk2x ce_l oe_l we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 c fg = 1010101010101010, hlat = 000, tlsz = 10, lram = 0, ldev = 0. n ote: |(bhi[2:0]) stands for the boolean ?or? of the entire bus bhi[2:0]. n ote: |(lhi[6:0]) stands for the boolean ?or? for the entire bus lhi[6:0]. n ote: each bit in bho[2:0] is the same logical signal. n ote: each bit in lho[1:0] is the same logical signal. phs_l sadr[23:0] ssf ssv ale_l search1 search2 z z z z z z z lho[1:0] 0 i(bhi[2:0]) 0 search3 |(lhi[6:0]) 0 bho[2:0] 0 cmdv cmd[1:0] cmd[10:2] 01 01 search1 search2 a b a b a b a b cmd[2] a b c d a b c d dq d1 d2 a b c d d3 a b a b 01 search3 (miss on this device.) (miss on this device.) (miss on this device; hit in block 0 or block 1.) figure 10-63. timing diagram for devices above the winning device in block number 2
cynse7012 8 document #: 38-02040 rev. *e page 90 of 137 cycle clk2x ce_l oe_l we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 c fg = 1010101010101010, hlat = 000, tlsz = 10, lram = 0, ldev = 0. n ote: |(bhi[2:0]) stands for the boolean ?or? of the entire bus bhi[2:0]. n ote: |(lhi[6:0]) stands for the boolean ?or? for the entire bus lhi[6:0]. n ote: each bit in bho[2:0] is the same logical signal. n ote: each bit in lho[1:0] is the same logical signal. phs_l sadr[23:0] ssf ssv ale_l search1 search2 z z z z z z lho[1:0] 0 (global winner.) i(bhi[2:0]) 0 (miss on this device.) search3 (hit but not winner.) |(lhi[6:0]) 0 bho[2:0] 0 a2 0 1 1 1 z z z z z z cmdv cmd[1:0] cmd[10:2] 01 01 search1 search2 a b a b a b a b cmd[2] a b c d a b c d dq d1 d2 a b c d d3 a b a b 01 search3 z 0 z z z figure 10-64. timing diagram for globally winning device in block number 2
cynse7012 8 document #: 38-02040 rev. *e page 91 of 137 cycle clk2x ce_l oe_l we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 c fg = 1010101010101010, hlat = 000, tlsz = 10, lram = 0, ldev = 0. n ote: |(bhi[2:0]) stands for the boolean ?or? of the entire bus bhi[2:0]. n ote: |(lhi[6:0]) stands for the boolean ?or? for the entire bus lhi[6:0]. n ote: each bit in bho[2:0] is the same logical signal. n ote: each bit in lho[1:0] is the same logical signal. phs_l sadr[23:0] ssf ssv ale_l search1 search2 z z z z z z lho[1:0] 0 (miss on this device.) i(bhi[2:0]) 0 (miss on this device.) search3 (miss on this device.) |(lhi[6:0]) 0 bho[2:0] 0 z cmdv cmd[1:0] cmd[10:2] 01 01 search1 search2 a b a b a b a b cmd[2] a b c d a b c d dq d1 d2 a b c d d3 a b a b 01 search3 figure 10-65. timing diagram for devices below the winning device in block number 2
cynse7012 8 document #: 38-02040 rev. *e page 92 of 137 cycle clk2x ce_l oe_l we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 c fg = 1010101010101010, hlat = 000, tlsz = 10, lram = 0, ldev = 0. n ote: |(bhi[2:0]) stands for the boolean ?or? of the entire bus bhi[2:0]. n ote: |(lhi[6:0]) stands for the boolean ?or? for the entire bus lhi[6:0]. n ote: each bit in bho[2:0] is the same logical signal. n ote: each bit in lho[1:0] is the same logical signal. phs_l sadr[23:0] ssf ssv ale_l search1 search2 z z z z z z lho[1:0] 0 (miss on this device.) i(bhi[2:0]) 0 (miss on this device.) search3 (miss on this device.) |(lhi[6:0]) 0 bho[2:0] 0 z cmdv cmd[1:0] cmd[10:2] 01 01 search1 search2 a b a b a b a b cmd[2] a b c d a b c d dq d1 d2 a b c d d3 a b a b 01 search3 figure 10-66. timing diagram for devices above the winning device in block number 3
cynse7012 8 document #: 38-02040 rev. *e page 93 of 137 cycle clk2x ce_l oe_l we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 c fg = 1010101010101010, hlat = 000, tlsz = 10, lram = 0, ldev = 0. n ote: |(bhi[2:0]) stands for the boolean ?or? of the entire bus bhi[2:0]. n ote: |(lhi[6:0]) stands for the boolean ?or? for the entire bus lhi[6:0]. n ote: each bit in bho[2:0] is the same logical signal. n ote: each bit in lho[1:0] is the same logical signal. phs_l sadr[23:0] ssf ssv ale_l search1 search2 z z z z z z lho[1:0] 0 (hit but not global i(bhi[2:0]) 0 (global winner.) search3 (miss on this device.) |(lhi[6:0]) 0 bho[2:0] 0 a1 0 z 1 1 1 z z z z z winner.) cmdv cmd[1:0] cmd[10:2] 01 01 search1 search2 a b a b a b a b cmd[2] a b c d a b c d dq d1 d2 a b c d d3 a b a b 01 search3 0 z figure 10-67. timing diagram for globally winning device in block number 3
cynse7012 8 document #: 38-02040 rev. *e page 94 of 137 cycle clk2x ce_l oe_l we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 c fg = 1010101010101010, hlat = 000, tlsz = 10, lram = 0, ldev = 0. n ote: |(bhi[2:0]) stands for the boolean ?or? of the entire bus bhi[2:0] n ote: |(lhi[6:0]) stands for the boolean ?or? for the entire bus lhi[6:0] n ote: each bit in bho[2:0] is the same logical signal. n ote: each bit in lho[1:0] is the same logical signal. phs_l sadr[23:0] ssf ssv ale_l search search2 z z z z z z lho[1:0] 0 i(bhi[2:0]) 0 search3 |(lhi[6:0]) 0 bho[2:0] 0 z cmdv cmd[1:0] cmd[10:2] 01 01 search1 search2 a b a b a b a b cmd[2] a b c d a b c d dq d1 d2 a b c d d3 a b a b 01 search3 (miss on this device.) (miss on this device.) (miss on this device.) figure 10-68. timing diagram for devices below the winning device in block number 3 except device 30 (the last device)
cynse7012 8 document #: 38-02040 rev. *e page 95 of 137 the following is the sequence of operation for a single 288-bit search command (also refer to ?commands and command parameters? on page 22). cycle a : the host asic drives the cmdv high and applies search command code (10) on cmd[1:0] signals. {cmd[10], cmd[5:3]} signals must be driven with the index to the gmr pair used for bits [287:144] of the data being searched. dq[71:0] must be driven with the 72-bit data ([287:216])to be compared to all locations 0 in the four 72-bits-word page. the cmd[2] signal must be driven to logic 1. note . cmd[2] = 1 signals that the search is a x288-bit search. cmd[8:6] is ignored in this cycle. cycle b : the host asic continues to drive the cmdv high and applies search command (10) on cmd[1:0]. the dq[71:0] is driven with the 72-bit data ([215:144]) to be compared to all locations 1 in the four 72-bits-word page. cycle clk2x ce_l oe_l we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 c fg = 1010101010101010, hlat = 000, tlsz = 10, lram = 1, ldev = 1. n ote: |(bhi[2:0]) stands for the boolean ?or? of the entire bus bhi[2:0]. n ote: |(lhi[6:0]) stands for the boolean ?or? for the entire bus lhi[6:0]. n ote: each bit in bho[2:0] is the same logical signal. n ote: each bit in lho[1:0] is the same logical signal. phs_l sadr[23:0] ssf ssv ale_l search1 search2 z 0 0 |(lhi[6:0)] (hit on some device i(bhi[2:0]) 0 (hit on some device search3 (hit on some device 0 bho[2:0] 0 z 0 1 above.) above.) above.) cmdv cmd[1:0] cmd[10:2] 01 01 search1 search2 a b a b a b a b cmd[2] a b c d a b c d dq d1 d2 a b c d d3 a b a b 01 search3 lho[1:0] 0 z z 0 0 0 z 0 z 1 1 z z 0 z 0 0 z 0 z 0 0 z figure 10-69. timing diagram of the last device in block number 3 (device 30 in the table)
cynse7012 8 document #: 38-02040 rev. *e page 96 of 137 cycle c : the host asic drives the cmdv high and applies search command code (10) on cmd[1:0] signals. {cmd[10], cmd[5:3]} signals must be driven with the index to the gmr pair used for the bits [143:0] of the data being searched. cmd[8:6] signals must be driven with the bits that will be driven by this device on sadr[23:21] if it has a hit. dq[71:0] must be driven with the 72-bit data ([143:72]) to be compared to all locations 2 in the four 72-bits-word page. the cmd[2] signal must be driven to logic 0. cycle b : the host asic continues to drive the cmdv high and continues to apply search command code (10) on cmd[1:0]. cmd[8:6] signals must be driven with the index of the ssr that will be used for storing the address of the matching entry and the hit flag (see page 16 for a description of ssr[0:7]). the dq[71:0] is driven with the 72-bit data ([71:0]) to be compared t o all locations 3 in the four 72-bits-word page. cmd[5:2] is ignored because the learn instruction is not supported for x288 tabl es. note . for 288-bit searches, the host asic must supply four distinct 72-bit data words on dq[71:0] during cycles a, b, c, and d. the gmr index in cycle a selects a pair of gmrs in each of the 31 devices that apply to dq data in cycles a and b. the gmr index in cycle c selects a pair of gmrs in each of the 31 devices that apply to dq data in cycles c and d. the logical 288-bit search operation is as shown in figure 10-70 . the entire table of 288-bit entries is compared to a 288-bit word k that is presented on the dq bus in cycles a, b, c, and d of the command using the gmr and local mask bits. the gmr is the 288-bit word specified by the two pairs of gmrs selected by the gmr indexes in the command?s cycles a and c in each of the 31 devices. the 288-bit word k that is presented on the dq bus in cycles a, b, c, and d of the command is compared to each entry in the table starting at location 0. the first matching entry?s location address l is the winning address that is driven as part of the sram address on the sadr[23:0] lines (see see ?sram addressing? on page 105). note . the matching address is always going to be location 0 in a four-entry page for 288-bit search (two lsbs of the matching index will be 00). the search command is a pipelined operation and executes a search at one-fourth the rate of the frequency of clk2x for 288- bit searches in x288-configured tables. the latency of sadr, ce_l, ale_l, we_l, ssv, and ssf from the 288-bit search command (measured in clk cycles) from the clk2x cycle that contains the c and d cycles is shown in table 10-32 . the latency of a search from command to sram access cycle is 6 for only a single device in the table and tlsz = 10. in addition , ssv and ssf shift further to the right for different values of hlat, as specified in table 10-33 . table 10-32. the latency of search from cycles c and d to sram access cycle number of devices max table size latency in clk cycles 1 (tlsz = 00) 16k 288 bits 4 1?8 (tlsz = 01) 128k 288 bits 5 1?31 (tlsz = 10) 496k 288 bits 6 table 10-33. shift of ssf and ssv from sadr hlat number of clk cycles 000 0 001 1 010 2 011 3 cfg = 1010101010101010 287 0 location 0 4 8 12 507900 (288-bit configuration) address k gmr 287 0 (first matching entry) l a b 01 c d 23 must be same in each of the 31 devices figure 10-70. x288 table with 31 devices
cynse7012 8 document #: 38-02040 rev. *e page 97 of 137 10.6.10 mixed-size searches on tables configured with different widths using a cynse70128 with cfg_l low this subsection will cover mixed searches (72, 144, and 288) with tables of different widths (72, 144, 288). the sample operation shown is for a single device with cfg = 1010010100000000 containing three tables of 72, 144, and 288 widths. the operation can be generalized to a block of 8?31 devices using four blocks; the timing and the pipeline operation is the sam e as described previously for fixed searches on a table of one-width-size. figure 10-71 shows three sequential searches: first, a 72-bit search on the table configured as 72, then a 144-bit search on a table configured as 144, and finally a 288-bit search on the table configured as 288 bits that each results in a hit. note . the dq[71:70] will be 00 in each of the two a and b cycles of the 72-bit search (search1). dq[71:70] is 01 in each of the a and b cycles of the 144-bit search (search2). dq[71:70] is 10 in each of the a, b, c, and d cycles of the 288-bit search (search3). by having table designation bits, the cynse70128 enables the creation of many tables in a bank of nses of different widths. figure 10-72 shows the sample table. two bits in each 72-bit entry will need to designated as the table number bits. one example choice can be the 00 values for the table configured as 72, 01 values for tables configured as 144, and 10 values for tables configured as 288. for the above explanation, it is further assumed that bits [71:70] for each entry will be designed as such table designation bits. 100 4 101 5 110 6 111 7 table 10-33. shift of ssf and ssv from sadr (continued) hlat number of clk cycles cycle clk2x cmdv cmd[1:0] ce_l oe_l cmd[10:2] we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 cfg = 1010101010101010, hlat = 010, tlsz = 00, lram = 1, ldev = 1. phs_l sadr[23:0] ssf ssv ale_l search1 search2 a2 01 01 search1 search3 a b a b a b a b 0 1 0 10 0 1 1 0 1 0 ab a b a b c d dq d1 d3 cmd[2] 101 1 0 1 a3 search2 01 d2 1 1 0 0 0 0 1 0 1 x72 hit x144 hit search2 x288 hit a1 a3 figure 10-71. timing diagram for mixed search (one device)
cynse7012 8 document #: 38-02040 rev. *e page 98 of 137 10.6.11 mixed-size searches on tables configured to different widths using a cynse70128 with cfg_l high this subsection will cover the mixed-size searches (72, 144, and 288) with tables of different widths (72, 144, 288) with cfg_l set high. the previous subsection described searches on tables of different widths using table designation bits in the data array. this can be wasteful of the bits in the data array. in order to avoid the waste of these bits and yet suppor t up to three tables of 72, 144, and 288, the cmd[2] and cmd[9] (in cfg_l high mode) in cycle a of the command can be used as shown in table 10-34 . 10.7 lram and ldev description when nses are cascaded using multiple cynse70128s, the sadr, ce_l, and we_l (three-state signals) are all tied together. in order to eliminate external pull-up and pull downs, one device in a bank is designated as the default driver. for non-search or non-learn cycles (see ?learn command? on page 98) or search cycles with a global miss, the sadr, ce_l, and we_l signals are driven by the device with the lram bit set. it is important that only one device in a bank of nses that are cascaded have t his bit set. failure to do so will cause contention on sadr, ce_l, we_l and can potentially cause damage to the device(s). similarly, when nses using multiple cynse70128s are casc aded, ssf and ssv (also three-state signals) are tied together. in order to eliminate external pull-up and pull downs, one device in a bank is designated as the default driver. for nonsearch cyc les or search cycles with a global miss the ssf and ssv signals are driven by the device with the ldev bit set. it is important tha t only one device in a bank of nses that are cascaded together have this bit set. failure to do so will cause contention on ssv and ssf and can potentially cause damage to the device(s). 10.8 learn command bit[0] of each 72-bit data location specifies whether an entry in the database is occupied. if all the entries in a device are occupied, the device asserts fulo signal to inform the downstream devices that it is full. the result of this communication between depth - cascaded devices determines the global full signal for the entire table. the full signal in the last device determines the fullness of the depth-cascaded table. the device contains 16 pairs of internal, 72-bit-wide comparand registers that store the comparands as the device executes searches. on a miss by the search signalled to asic through the ssv and ssf signals (ssv = 1, ssf = 0), the host asic can apply the learn command to learn the entry from a comparand register to the next-free location (see ?nfa register? on page 19). the nfa updates to the next-free location following each write or learn command. in a depth-cascaded table, only a single device will learn the entry through the application of a learn instruction. the determ ination of which device is going to learn is based on the fuli and fulo signalling between the devices. the first non-full device learn s the entry by storing the contents of the specified comp arand registers to the location(s) pointed to by nfa. in a 72-configured table the learn command writes a single 72-bit location. in a 144-configured table the learn command writes the next even and odd 72-bit locations. in 144-bit mode, bit[0] of the even and odd 72-bit locations is 0, which indicat es that they are cascaded empty, or 1, which indicates that they are occupied. table 10-34. searches with cfg_l set high cmd[9] cmd[2] search 0 0 search 72-bit-configured partitions only. 1 0 search 144-bit-configured partitions only. x 1 cycles a and b for searching 288-bit-configured partitions. x 0 cycles c and d for searching 288-bit-configured partitions. 4 k 32 k 72 8 k 144 cfg = 10 10 01 01 00 00 00 00 288 figure 10-72. multiwidth configurations example
cynse7012 8 document #: 38-02040 rev. *e page 99 of 137 the global full signal indicates to the table controller (the host asic) that all entries within a block are occupied and that no more entries can be learned. the cynse70128 updates the signal after each write or learn command to a data array. the learn command generates a write cycle to the external sram, also using the nfa register as part of the sram address (see ?sram addressing? on page 105). the learn command is supported on a single block containing up to eight devices if the table is configured either as a 72 or a 144. the learn command is not supported for x288-configured ta bles. additionally, learn is not supported when the device is operating at > 83-mhz clk1x (166-mhz clk2x). learn is a pipelined operation and lasts for two clk cycles, as shown in figure 10-73 where tlsz = 00, and figure 10-74 and figure 10-75 where tlsz = 01. figure 10-74 and figure 10-75 assume that the device performing the learn operation is not the last device in the table and has its lram bit set to 0. note . the oe_l for the device with the lram bit set goes high for two cycles for each learn (one during the sram write cycle, and one the cycle before). the latency of the sram write cycle from the second cycle of the instruction is shown in table 10-35 . cycle learn1 learn2 clk2x cmdv cmd[1:0] dq sadr[23:0] cmd[10:2] x we_l oe_l a1 a2 x xxx x tlsz = 00, lram = 1, ldev = 1. 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 x x x 1a 1b comp1 comp2 x phs_l 1 1 z z zz z 0 0 0 0 0 0 0 ssv ssf 1 0 1 1 ce_l figure 10-73. timing diagram of learn (tlsz = 00)
cynse7012 8 document #: 38-02040 rev. *e page 100 of 137 cycle learn1 learn2 clk2x cmdv cmd[1:0] dq sadr[23:0] ce_l cmd[10:2] x we_l oe_l a1 a2 x xxx x tlsz = 01, lram = 0, ldev = 0. 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 x x x 1a 1b comp1 comp2 x phs_l z z z z z z z 0 0 z z ssv ssf z 0 0 figure 10-74. timing diagram of learn (except on the last device [tlsz = 01])
cynse7012 8 document #: 38-02040 rev. *e page 101 of 137 the learn operation lasts two clk cycles. the sequence of operation is as follows. cycle 1a : the host asic applies the learn instruction on cmd[1:0] using cmdv = 1. the cmd[5:2] field specifies the index of the comparand register pair that will be written in the data array in the 144-bit-configured table. for a learn in a 72-bit- configured table, the even-numbered comparand specified by this index will be written. cmd[8:6] carries the bits that will be driven on sadr[23:21] in the sram write cycle. cycle 1b : the host asic continues to drive the cmdv to 1, the cmd[1:0] to 11, and the cmd[5:2] with the comparand pair index. cmd[6] must be set to 0 if the learn is being performed on a 72-bit-configured table, and to 1 if the learn is being performed on a 144-bit-configured table. table 10-35. latency of sram write cycl e from second cycle of learn instruction number of devices latency in clk cycles 1 (tlsz = 00) 4 1?8 (tlsz = 01) 5 1?31 (tlsz = 10) 6 cycle learn1 learn2 clk2x cmdv cmd[1:0] dq sadr[23:0] ce_l cmd[10:2] x we_l oe_l x xxx x tlsz = 01, lram = 1, ldev = 1. 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 x x x 1a 1b comp1 comp2 x phs_l 1 1 z z z z z 0 zz zz 0 0 ssv ssf 1 1 1 0 z 1 1 figure 10-75. timing diagram of learn on device number 7 (tlsz = 01)
cynse7012 8 document #: 38-02040 rev. *e page 102 of 137 cycle 2 : the host asic drives the cmdv to 0. at the end of cycle 2, a new instruction can begin. the latency of the sram write is the same as the search to the sram read cycle. it is measured from the second cycle of the learn instruction. 11.0 depth-cascading the nse application can depth-cascade the devices to various table sizes of different widths (72 bits, 144 bits, or 288 bits). the devices perform all the necessary arbitration to decide whic h device will drive the sram bus. the latency of the searches increases as the table size increases; the search rate remains constant. 11.1 depth-cascading up to eight devices (one block) figure 11-1 shows how up to eight devices can be cascaded to form 512k 72, 256k 144, or 128k 288 tables. it also shows the interconnection between the devices for depth-cascading. each nse asserts the lho[1] and lho[0] signals to inform downstream devices of its result. the lhi[6:0] signals for a device are connected to lho signals of the upstream devices. the host asic must program the tlsz to 01 for each of up to eight devices in a block. only a single device drives the sram bus in any single cycle.
cynse7012 8 document #: 38-02040 rev. *e page 103 of 137 11.2 depth-cascading up to 31 devices (four blocks) figure 11-2 shows how to cascade up to four blocks. each block contains up to eight cynse70128 devices except the last, and the interconnection within each was shown in the previous subsection with the cascading of up to eight devices in a block. note . the interconnection between blocks for depth-cascading is important. for each search, a block asserts bho[2], bho[1], and bho[0]. the bho[2:0] signals for a block are the signals taken only from the last device in the block. for all other devices wi thin that block, these signals stay open and floating. the host asic must program the table size (tlsz) field to 10 in each of the devices for cascading up to 31 devices (in up to four blocks). lho[0] 6543210 lhi lho[0] 65 32 10 lhi lho[1] 6543 210 lhi lho[0] 654321 0 lhi lho[0] 654 3210 lhi lho[0] 65 4 3210 lhi lho[0] 654 32 10 lhi bho[0] 65 4 3210 lhi lho[0] lhi lhi lhi lho[1] lho[1] lho[1] bho[1] bho[0] bho[1] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] dq[71:0] sram lho[1] lho[0] cynse70128 #0 cynse70128 #1 cynse70128 #2 cynse70128 #3 cynse70128 #4 cynse70128 #5 cynse70128 #6 cynse70128 #7 4 bho[2] bho[2] cmdv cmd[10:0] ssf, ssv figure 11-1. depth-cascading to form a single block
cynse7012 8 document #: 38-02040 rev. *e page 104 of 137 11.3 depth-cascading for a full signal bit[0] of each of the 72-bit entries is designated as a special bit (1 = occupied; 0 = empty). for each learn or pio write to t he data array, each device asserts fulo[1] and fulo[0] if it does not have any empty locations within it (see figure 11-3 ). each device combines the fulo signals from the devices above it with its own full status to generate a full signal that gives the fu ll status of the table up to the device asserting the full signal. figure 11-3 shows the hardware connection diagram for generating the full signal that goes back to the asic. in a depth-cascaded block of up to eight devices, the full signal from the last dev ice should be fed back to the asic controller to indicate the fullness of the table. the full signal of the other devices should be left open. note . the learn instruction is supported for only up to eight devices, whereas full cascading is allowed only for one block in tables containing more than eight devices. in tables for which a learn instruction is not going to be used, the bit[0] of ea ch 72- bit entry should always be set to 1. bho[2] block of 8 cynse70128s block 0 (devices 0?7) bho[1] bho[0] bhi[2] bhi[1] bhi[0] bhi[2] block of 7 cynse70128s block 3 (devices 24-30) bhi[1] bhi[0] gnd bho[2] bho[1] bho[0] bhi[2] bhi[1] bhi[0] gnd bhi[2] bhi[1] bhi[0] gnd block of 8 cynse70128s block 1 (devices 8?15) block of 8 cynse70128s block 2 (devices 16?23) dq[71:0] sram bho[2] bho[2] bho[1] bho[1] bho[0] bho[0] cmd[10:0], cmdv ssf, ssv figure 11-2. depth-cascading four blocks
cynse7012 8 document #: 38-02040 rev. *e page 105 of 137 12.0 sram addressing table 12-1 describes the commands used to generate addresses on the sram address bus. the index [15:0] field contains the address of a 72-bit entry that results in a hit in 72-bit-configured quadrant. it is the address of the 72-bit entry that lies at the 144-bit page, and the 288-bit page boundaries in 144-bit- and 288-bit-configured quadrants, respectively. ?registers? on page 15 of this specification, describes the nfa and ssr registers. adr[15:0] contains the address supplied on the dq bus during pio access to the cynse70128. command bits 8, 7, and 6 {cmd[8:6]} are passed from the command to the sram address bus. see ?commands? on page 21, for more information. id[4:0] is the id of the device driving the sram bus (see ?pinout description? on page 130 for more information). fulo[0] 654 3210 fuli fulo[0] 65 4 3 2 1 0 fuli fulo[1] 65 4 3 2 1 0 fuli fulo[0] 65 4 3 2 1 0 fuli fulo[0] 6543210 fuli fulo[0] 65 4 321 0 fuli 6 5 4 3210 fuli 65 4 3 210 fulo[0] fuli fuli fuli fulo[1] fulo[1] fulo[1] dq[71:0] fulo[1] fulo[0] v ddq v ddq v ddq v ddq v ddq v ddq full full full full full full full full v ddq cynse70128 cynse70128 cynse70128 cynse70128 cynse70128 cynse70128 cynse70128 cynse70128 fuli fulo[0] figure 11-3. full generation in a cascaded table
cynse7012 8 document #: 38-02040 rev. *e page 106 of 137 12.1 generating an sram bus address 12.2 sram pio access the remainder of this section describes sram read and sram write operations. sram read enables read access to the off-chip sram containing associative data. the latency from the issuance of the read instruction to the address appearing on the sram bus is the same as the latency of the search instruction and will be depend on the value programmed for the tlsz parameter in the device configuration register. the latency of the ack from the read instruction is the same as the latency of the search instruction to the sram address plus the hlat programmed in the configu- ration register. note . sram read is a blocking operation?no new instruction can begin until the ack is returned by the selected device performing the access. sram write enables write access to the off-chip sram containing associative data. the latency from the second cycle of the write instruction to the address appearing on the sram bus is the same as the latency of the search instruction and will depend on the tlsz value parameter programmed in the device configuration register. note . sram write is a pipelined operation?new instruction can begin right after the previous command has ended. 12.3 sram read with a table of one device sram read enables read access to the off-chip sram containing associative data. the latency from the issuance of the read instruction to the address appearing on the sram bus is the same as the latency of the search instruction and will depend on the tlsz value parameter programmed in the device configuration register. the latency of the ack from the read instruction is the same as the latency of the search instruction to the sram address plus the hlat programmed in the configuration register. the following explains the sram read operation in a table with only one device that has the following parameters: tlsz = 00, hlat = 000, lram = 1, and ldev = 1. figure 12-1 shows the associated timing diagram. for the following description, the selected device refers to the only device in the table because it is the only device to be accessed. cycle 1a : the host asic applies the read instruction on the cmd[1:0] using cmdv = 1. the dq bus supplies the address, with dq[20:19] set to 10, to select the sram address. the host asic selects the device for which the id[4:0] matches the dq[25:21] lines. during this cycle, the host asic also supplies sadr[23:21] on cmd[8:6]. cycle 1b : the host asic continues to apply the read instruction on the cmd[1:0] using cmdv = 1. the dq bus supplies the address with dq[20:19] set to 10 to select the sram address. cycle 2 : the host asic floats dq[71:0] to a three-state condition. cycle 3 : the host asic keeps dq[71:0] in a three-state condition. cycle 4 : the selected device starts to drive dq[71:0] and drives ack from high-z to low. cycle 5 : the selected device drives the read address on sadr[23:0]; it also drives ack high, ce_l low, and ale_l low. cycle 6 : the selected device drives ce_l high, ale_l high, the sadr bus, the dq bus in a three-state condition, and ack low. at the end of cycle 6, the selected device floats ack in a three-state condition, and a new command can begin. table 12-1. sram address command sram operation 23 22 21 [20:16] [15:0] search read c8 c7 c6 id[4:0] index[15:0] learn write c8 c7 c6 id[4:0] nfa[15:0] pio read read c8 c7 c6 id[4:0] adr15:0] pio write write c8 c7 c6 id[4:0] adr[15:0] indirect access write/read c8 c7 c6 id[4:0] ssr[15:0]
cynse7012 8 document #: 38-02040 rev. *e page 107 of 137 12.4 sram read with a table of up to eight devices the following explains the sram read operation completed through a table of up to eight devices using the following parameters: tlsz = 01. figure 12-2 diagrams a block of eight devices. the following assumes that sram access is successfully achieved through cynse70128 device number 0. figure 12-3 and figure 12-4 show timing diagrams for device number 0 and device number 7, respectively. cycle 1a : the host asic applies the read instruction on cmd[1:0] using cmdv = 1. the dq bus supplies the address, with dq[20:19] set to 10, to select the sram address. the host asic selects the device for which id[4:0] matches the dq[25:21] lines. during this cycle the host asic also supplies sadr[23:21] on cmd[8:6]. cycle 1b : the host asic continues to apply the read instruction on cmd[1:0] using cmdv = 1. the dq bus supplies the address, with dq[20:19] set to 10 to select the sram address. cycle 2 : the host asic floats dq[71:0] to a three-state condition. cycle 3 : the host asic keeps dq[71:0] in a three-state condition. cycle 4 : the selected device starts to drive dq[71:0]. cycle 5 : the selected device continues to drive dq[71:0] and drives ack from high-z to low. cycle 6 : the selected device drives the read address on sadr[23:0]. it also drives ack high, ce_l low, we_l high, and ale_l low. cycle 7 : the selected device drives ce_l, ale_l, we_l, and dq bus in a three-state condition. it continues to drive ack low. at the end of cycle 7, the selected device floats ack in three-state condition and a new command can begin. cycle clk2x dq read address ack oe_l we_l ale_l sadr address 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 tlsz = 00, hlat = 000, lram = 1, ldev = 1. phs_l cmd[10:2] a b z z 0 1 0 z z 0 0 1 z 1 z 1 ssv 0 0 ssf ce_l 1 0 1 dq driven by cynse70128 cmdv cmd[1:0] figure 12-1. sram read access (tlsz = 00, hlat = 000, lram = 1, ldev = 1)
cynse7012 8 document #: 38-02040 rev. *e page 108 of 137 lho[0] 6543210 lhi lho[0] 65 32 10 lhi lho[1] 6543 210 lhi lho[0] 654321 0 lhi lho[0] 654 3210 lhi lho[0] 65 4 3210 lhi lho[0] 654 32 10 lhi bho[0] 65 4 3210 lhi lho[0] lhi lhi lhi lho[1] lho[1] lho[1] bho[1] bho[0] bho[1] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] dq[71:0] sram lho[1] lho[0] cynse70128 #0 cynse70128 #1 cynse70128 #2 cynse70128 #3 cynse70128 #4 cynse70128 #5 cynse70128 #6 cynse70128 #7 4 bho[2] bho[2] cmdv cmd[10:0] ssf, ssv figure 12-2. table of a block of eight devices
cynse7012 8 document #: 38-02040 rev. *e page 109 of 137 cycle clk2x cmdv cmd[1:0] dq read address oe_l we_l ce_l sadr address 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 tlsz = 01, hlat = 000, lram = 0, ldev = 0. phs_l cmd[10:2] a b z z z z 0 z z z ssv z ssf ale_l z 0 z z 0 0 1 z z 1 cycle 7 dq driven by selected cynse70128 figure 12-3. sram read through device number 0 in a block of eight devices
cynse7012 8 document #: 38-02040 rev. *e page 110 of 137 12.5 sram read with a table of up to 31 devices the following explains the sram read operation accomplished through a table of up to 31 devices, using the following param- eters: tlsz = 10. the diagram of such a table is shown in figure 12-5 . the following assumes that sram access is being accomplished through cynse70128 device number 0, that device number 0 is the selected device. figure 12-6 and figure 12- 7 show the timing diagrams for device number 0 and device number 30, respectively. cycle 1a : the host asic applies the read instruction to cmd[1:0] using cmdv = 1. the dq bus supplies the address, with dq[20:19] set to 10, to select the sram address. the host asic selects the device for which the id[4:0] matches the dq[25:21] lines. during this cycle, the host asic also supplies sadr[23:21] on cmd[8:6]. cycle 1b : the host asic continues to apply the read instruction to cmd[1:0] using cmdv = 1. the dq bus supplies the address, with dq[20:19] set to 10, to select the sram address. cycle 2 : the host asic floats dq[71:0] to a three-state condition. cycle 3 : the host asic keeps dq[71:0] in a three-state condition. cycle 4 : the selected device starts to drive dq[71:0]. cycles 5 to 6 : the selected device continues to drive dq[71:0]. cycle 7 : the selected device continues to drive dq[71:0] and drives an sram read cycle. cycle 8 : the selected device drives ack from z to low. cycle 9 : the selected device drives ack to high. cycle 10 : the selected device drives ack from high to low. at the end of cycle 10, the selected device floats ack in a three-state condition. cycle clk2x cmdv cmd[1:0] dq read address oe_l we_l ce_l sadr 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 tlsz = 01, hlat = 000, lram = 1, ldev = 1. phs_l cmd[10:2] a b z 0 1 z z 1 1 ssv z ssf ale_l 1 z 1 z z z ack z 1 figure 12-4. sram read timing for device number 7 in a block of eight devices
cynse7012 8 document #: 38-02040 rev. *e page 111 of 137 bho[2] block of 8 cynse70128s block 0 (devices 0?7) bho[1] bho[0] bhi[2] bhi[1] bhi[0] bhi[2] block of 7 cynse70128s block 3 (devices 24?30) bhi[1] bhi[0] gnd bho[2] bho[1] bho[0] bhi[2] bhi[1] bhi[0] gnd bhi[2] bhi[1] bhi[0] gnd block of 8 cynse70128s block 1 (devices 8?15) block of 8 cynse70128s block 2 (devices 16?23) dq[71:0] sram bho[2] bho[2] bho[1] bho[1] bho[0] bho[0] cmd[10:0], cmdv ssf, ssv figure 12-5. table of 31 devices made of four blocks
cynse7012 8 document #: 38-02040 rev. *e page 112 of 137 cycle clk2x ce_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 tlsz = 10, hlat = 010, lram = 0, ldev = 0. phs_l sadr[23:0] ssf ssv z z z z cmdv cmd[1:0] cmd[10:2] 00 read a b address dq address 0 z z 1 we_l oe_l z ale_l z 0 z z z z z 1 0 0 ack dq driven by the selected cynse70128 figure 12-6. sram read through device number 0 in a block of 31 devices (device number 0 timing)
cynse7012 8 document #: 38-02040 rev. *e page 113 of 137 12.6 sram write with a table of one device sram write enables write access to the off-chip sram that contains associative data. the latency from the second cycle of the write instruction to the address appearing on the sram bus is the same as the latency of the search instruction, and will depen d on the tlsz value parameter programmed in the device configuration register. the following explains the sram write operation accomplished with a table of only one device of the following parameters: tlsz = 00, hlat = 000, lram = 1, and ldev = 1. figure 12-8 shows the timing diagram. for the following description the selected device refers to the only device in the table as it is the only device that will be accessed. cycle 1a : the host asic applies the write instruction on cmd[1:0] using cmdv = 1. the dq bus supplies the address with dq[20:19] set to 10 to select the sram address. the host asic selects the device for which the id[4:0] matches the dq[25:21] lines. the host asic also supplies sadr[23:21] on cmd[8:6] in this cycle. note . cmd[2] must be set to 0 for sram write because burst writes into the sram are not supported. cycle 1b : the host asic continues to apply the write instruction on cmd[1:0], using cmdv = 1. the dq bus supplies the address with dq[20:19] set to 10 to select the sram address. note . cmd[2] must be set to 0 for sram write because burst writes into the sram are not supported. cycle 2 : the host asic continues to drive dq[71:0]. the data in this cycle is not used by the cynse70128 device. cycle 3 : the host asic continues to drive dq[71:0]. the data in this cycle is not used by the cynse70128 device. at the end of cycle 3, a new command can begin. the write is a pipelined operation. the write cycle appears at the sram bus, however, with the same latency as that of a search instruction, as measured from the second cycle of the write command. cycle clk2x ce_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 t lsz = 10, hlat = 010, lram = 1, ldev = 1. phs_l sadr[23:0] ssf ssv 1 0 0 cmdv cmd[1:0] cmd[10:2] 00 read a b address dq z 1 we_l oe_l 0 ale_l 1 z 1 z ack z 1 1 z figure 12-7. sram read through device number 0 in a block of 31 devices (device number 30 timing)
cynse7012 8 document #: 38-02040 rev. *e page 114 of 137 12.7 sram write with a table of up to eight devices the following explains the sram write operation done through a table(s) of up to eight devices with the following parameters (tlsz = 01). the diagram of such a table is shown in figure 12-9 . the following assumes that sram access is done through cynse70128 device number 0. figure 12-10 and figure 12-11 show the timing diagram for device number 0 and device number 7, respectively. cycle 1a : the host asic applies the write instruction on cmd[1:0] using cmdv = 1. the dq bus supplies the address with dq[20:19] set to 10 to select the sram address. the host asic selects the device for which the id[4:0] matches the dq[25:21] lines. the host asic also supplies sadr[23:21] on cmd[8:6] in this cycle. note . cmd[2] must be set to 0 for sram write because burst writes into the sram are not supported. cycle 1b : the host asic continues to apply the write instruction on cmd[1:0] using cmdv = 1. the dq bus supplies the address with dq[20:19] set to 10 to select the sram address. note . cmd[2] must be set to 0 for sram write because burst writes into the sram are not supported. cycle 2 : the host asic continues to drive dq[71:0]. the data in this cycle is not used by the cynse70128 device. cycle 3 : the host asic continues to drive dq[71:0]. the data in this cycle is not used by the cynse70128 device. at the end of cycle 3, a new command can begin. the write is a pipelined operation. the write cycle appears at the sram bus, however, with the same latency as that of a search instruction, as measured from the second cycle of the write command. cycle clk2x cmdv cmd[1:0] dq write address ack oe_l we_l ale_l sadr address 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 tlsz = 00, hlat = 000, lram = 1, ldev = 1. phs_l cmd[10:2] a b x 0 1 z z 1 ssv 0 0 ssf ce_l 1 x x 1 0 0 0 figure 12-8. sram write access (tlsz = 00, hlat = 000, lram = 1, ldev = 1)
cynse7012 8 document #: 38-02040 rev. *e page 115 of 137 lho[0] 6543210 lhi lho[0] 65 32 10 lhi lho[1] 6543 210 lhi lho[0] 654321 0 lhi lho[0] 654 3210 lhi lho[0] 65 4 3210 lhi lho[0] 654 32 10 lhi bho[0] 65 4 3210 lhi lho[0] lhi lhi lhi lho[1] lho[1] lho[1] bho[1] bho[0] bho[1] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] dq[71:0] sram lho[1] lho[0] cynse70128 #0 cynse70128 #1 cynse70128 #2 cynse70128 #3 cynse70128 #4 cynse70128 #5 cynse70128 #6 cynse70128 #7 4 bho[2] bho[2] cmdv cmd[10:0] ssf, ssv figure 12-9. table of a block of eight devices
cynse7012 8 document #: 38-02040 rev. *e page 116 of 137 cycle clk2x ce_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 t lsz = 01, hlat = xxx, lram = 0, ldev = 0. phs_l sadr[23:0] ssf ssv z z z cmdv cmd[1:0] cmd[10:2] 01 write a b address dq address 0 we_l oe_l z ale_l z z z ack x x z z z 0 z z 0 z figure 12-10. sram write through device number 0 in a block of eight devices
cynse7012 8 document #: 38-02040 rev. *e page 117 of 137 12.8 sram write with table(s) of up to 31 devices the following explains the sram write operation done through a table(s) of up to 31 devices with the following parameters (tlsz = 10). the diagram of such table(s) is shown in figure 12-12 . the following assumes that sram access is done through cynse70128 device number 0?device 0 is the selected device. figure 12-13 and figure 12-14 show the timing diagram for device number 0 and device number 30, respectively. cycle 1a : the host asic applies the write instruction on cmd[1:0] using cmdv = 1. the dq bus supplies the address with dq[20:19] set to 10 to select the sram address. the host asic selects the device for which the id[4:0] matches the dq[25:21] lines. the host asic also supplies sadr[23:21] on cmd[8:6] in this cycle. note . cmd[2] must be set to 0 for sram write because burst writes into the sram are not supported. cycle 1b : the host asic continues to apply the write instruction on cmd[1:0] using cmdv = 1. the dq bus supplies the address with dq[20:19] set to 10 to select the sram address. note . cmd[2] must be set to 0 for sram write because burst writes into the sram are not supported. cycle 2 : the host asic continues to drive dq[71:0]. the data in this cycle is not used by the cynse70128 device. cycle 3 : the host asic continues to drive dq[71:0]. the data in this cycle is not used by the cynse70128 device. at the end of cycle 3, a new command can begin. the write is a pipelined operation. the write cycle appears at the sram bus, however, with the same latency as that of a search instruction, as measured from the second cycle of the write command. cycle clk2x ce_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 tlsz = 01, hlat = xxx, lram = 1, ldev = 1. phs_l sadr[23:0] ssf ssv 1 0 0 cmdv cmd[1:0] cmd[10:2] 01 write a b address dq z we_l oe_l 0 ale_l z z ack x x 1 0 1 1 z 1 1 z 1 figure 12-11. sram write timing for device number 7 in a block of eight devices
cynse7012 8 document #: 38-02040 rev. *e page 118 of 137 bho[2] block of 8 cynse70128s block 0 (devices 0?7) bho[1] bho[0] bhi[2] bhi[1] bhi[0] bhi[2] block of 7 cynse70128s block 3 (devices 24?30) bhi[1] bhi[0] gnd bho[2] bho[1] bho[0] bhi[2] bhi[1] bhi[0] gnd bhi[2] bhi[1] bhi[0] gnd block of 8 cynse70128s block 1 (devices 8?15) block of 8 cynse70128s block 2 (devices 16?23) dq[71:0] sram bho[2] bho[2] bho[1] bho[1] bho[0] bho[0] cmd[10:0], cmdv ssf, ssv figure 12-12. table of 31 devices (four blocks)
cynse7012 8 document #: 38-02040 rev. *e page 119 of 137 cycle clk2x ce_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 tlsz = 10, hlat = xxx, lram = 0, ldev = 0. phs_l sadr[23:0] ssf ssv z z z cmdv cmd[1:0] cmd[10:2] 01 write a b address dq address 0 we_l oe_l z ale_l z z z ack x x z z z 0 z z 0 z figure 12-13. sram write through device number 0 in a bank of 31 devices (device 0 timing)
cynse7012 8 document #: 38-02040 rev. *e page 120 of 137 cycle clk2x ce_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 tlsz = 10, hlat = xxx, lram = 1, ldev = 1. phs_l sadr[23:0] ssf ssv 1 0 0 cmdv cmd[1:0] cmd[10:2] 01 write a b address dq z we_l oe_l 0 ale_l z z ack x x 1 1 1 z 1 1 z 1 figure 12-14. sram write through device numb er 0 in a bank of 31 cynse70128 devices (device number 30 timing)
cynse7012 8 document #: 38-02040 rev. *e page 121 of 137 13.0 power cynse70128 has two separate power supplies, one for the core (v dd ) and another for the i/os (v ddq ). 13.1 power-up sequence proper power-up sequence is required to correctly initialize the cypress nses before functional access to the device can begin. rst_l and trst_l should be held low before the power supplies ramp-up. rst_l must be set low for a duration of time afterward and then set high. the following steps describe the proper power-up sequence. 1. set rst_l and trst_l low. 2. power up v dd , v ddq and start running clk1x when operating in clk1x mode or clk2x and phs_l when operating in clk2x mode. the order in which these signals (including v dd and v ddq ) are applied is not critical. 3. rst_l should be held low for 0.5ms (pll lock time requirement). in clk1x mode, the counting starts on the first rising edge of clk1x after both v dd and v ddq have reached their steady state voltages. in clk2x mode, the counting starts on the first rising edge of clk2x when phs_l is high, after both v dd and v ddq have reached their steady state voltages. 4. continue to hold rst_l low for a minimum of 32 clk1x cycles (when operating in clk1x mode) or 64 clk2x cycles (when operating in clk2x mode). set rst_l to high afterward to complete the power-up sequence. for jtag reset, trst_l can be brought high after v dd and v ddq have both reached their steady state voltages. figure 13-1 and figure 13-2 illustrate the proper sequences of the power-up operation figure 13-1. power-up sequence (clk2x) figure 13-2. power-up sequence (clk1x) vdd vddq 64 clk2x clk2x phs_l rst_l trst_l cycles pll lock time, 0.5ms vdd vddq pll lock time, 0.5ms 64 clk2x clk1x rst_l trst_l cycles
cynse7012 8 document #: 38-02040 rev. *e page 122 of 137 13.2 power consumption figure 13-3 depicts expected power consumption over a range of frequencies. the calculations assume 100% of the operations will be search operations. if an application includes other operations such as read or write, then power consumption will be lower. the worst case line indicates power consumption when the i/os switch 100% of the time. the other lines (all search hit and all search miss) assume the i/os switch 50% of the time. power consumption of cynse70128 0 2 4 6 8 10 12 0 102030405060708090100 fr e que nc y ( mhz ) power (w) absolute worst case (75c) all searches miss (75c) all searches hit (75c) figure 13-3. power consumption of cynse70128
cynse7012 8 document #: 38-02040 rev. *e page 123 of 137 14.0 application figure 14-1 shows how an nse subsystem can be formed using a host asic and an cynse70128 bank. it also shows how this nse subsystem is integrated in a switch or router. the cynse70128 can access synchronous and asynchronous srams by allowing the host asic to set the same hlat parameter in all nses within a bank of nses. 15.0 jtag (1149.1) testing the cynse70128 supports the test access port and boundary scan architecture as specified in the ieee jtag standard number 1149.1. the pin interface to the chip consists of five signals with the standard definitions: tck, tms, tdi, tdo, and trst_l. table 15-1 describes the operations that the test access port controller supports, and table 15-2 describes the tap device id register. note . to disable jtag functionality, connect the tck, tms and tdi pins to v ddq through a pull-up, and trst_l to ground through a pull-down. table 15-1. supported operations instruction type description sample/preload mandatory this operation loads the values of signals going to and from i/o pins into the boundary scan shift register to provide a snapshot of the normal functional operation. extest mandatory this operation uses boundary scan values shifted in from tap to test connectivity external to the device. bypass mandatory this operation loads a single bit shift register between tdi and tdo and provides a minimum- length serial path when no test operation is required idcode optional this operation selects the identification register between tdi and tdo and allows the ?idcode? to be read serially through tdo. clamp optional this operation drives preset values onto the outputs of devices. highz optional this operation leaves the device output pins in a high-impedance state. p r o g r a m m e m o r y n e t w o r k l i n e i n t e r f a c e s s y s t e m b u s s w i t c h p r o c e s s o r s w i t c h f a b r i c h o s t a s i c s e a r c h e n g i n e s r a m b a n k figure 14-1. sample switch/router using the cynse70128 device
cynse7012 8 document #: 38-02040 rev. *e page 124 of 137 16.0 electrical specifications this section describes the electrical specifications, capacitance, operating conditions, dc characteristics, and ac timing para m- eters for the cynse70128, as shown in table 16-1 and table 16-2 . table 15-2. tap device id register field range initial value description revision [31:28] 0001 revision number. this is the current device revision number. numbers start from 1 and increment by 1 for each revision of the device. part number [27:12] 0000 0000 0000 0100 this is the part number for the device. mfid [11:1] 000_1101_1100 manufacturer id. this field is the same as the manufacturer id used in the tap controller. lsb [0] 1 least significant bit. table 16-1. dc electrical characteristics for cynse70128 parameter description test condition min. max. unit i li input leakage current v ddq = v ddq max, v in = 0 to v ddq max ?10 10 m a i lo output leakage current v ddq = v ddq max, v in =0 to v ddq max ?10 10 m a v il input low voltage (v ddq = 3.3v) ?0.3 0.8 v v ih input high voltage (v ddq = 3.3v) 2.0 v ddq + 0.3 v v il input low voltage (v ddq = 2.5v) ?0.3 0.7 v v ih input high voltage (v ddq = 2.5v) 1.7 v ddq + 0.3 v v ol output low voltage (v ddq = 3.3v) v ddq = v ddq min, i ol = 16ma 0.4 v v oh output high voltage (v ddq = 3.3v) v ddq = v ddq min, i oh = 8ma 2.4 v v ol output low voltage (v ddq = 2.5v) v ddq = v ddq min, i ol = 8ma 0.4 v v oh output high voltage (v ddq = 2.5v) v ddq = v ddq min, i oh = 8ma 2.0 v i dd2 3.3v supply current at v dd max 100 mhz search rate, l out = 0ma 350 ma i dd2 3.3v supply current at v dd max 83 mhz search rate, l out =0ma 300 ma i dd2 3.3v supply current at v dd max 66 mhz search rate, l out = 0ma 240 ma i dd2 2.5v supply current at v dd max 100 mhz search rate, l out =0ma 350 ma i dd2 2.5v supply current at v dd max 83 mhz search rate, l out = 0ma 300 ma i dd2 2.5v supply current at v dd max 66 mhz search rate, l out = 0ma 240 ma i ddl 1.65v supply current at v dd max 100 mhz search rate 6.0 a i ddl 1.5v supply current at v dd max 83 mhz search rate 5.0 a i ddl 1.5v supply current at v dd max 66 mhz search rate 4.0 a parameter description max. unit c in input capacitance 6 pf [13] c out output capacitance 6 pf [14] notes: 13. f = 1 mhz, v in = 0 v. 14. f = 1 mhz, v out = 0 v.
cynse7012 8 document #: 38-02040 rev. *e page 125 of 137 17.0 ac timing waveforms table 17-1 and table 17-2 show the ac timing parameters for the cynse70128 device; table 17-3 shows the same parameters but for 2.5v. table 16-2. operating conditions for cynse70128 parameter description min. max. unit v ddq operating voltage for i/o (3.3v) 3.1 3.5 v v ddq operating voltage for i/o (2.5v) 2.375 2.625 v v dd operating supply voltage 1.425 (for clk1x = 83 mhz) 1.568 (for clk1x = 100 mhz) 1.575 (for clk1x = 83 mhz) 1.733 (for clk1x = 100 mhz) v v ih input high voltage [15] (3.3v) 2.0 v ddq + 0.3 v v ih input high voltage [15] (2.5v) 1.7 v ddq + 0.3 v v il input low voltage [16] (3.3v) ?0.3 0.8 v v il input low voltage [16] (2.5)v ?0.3 0.7 v t a ambient operating temperature (commercial) 0+70 c t a ambient operating temperature (industrial) ?40 +85 c supply voltage tolerance ?5 +5 % table 17-1. ac timing parameters with clk2x row parameter description cynse70128 -66 cynse70128 -83 cynse70128 -100 unit (v ddq = 3.3v, 2.5v) (v ddq = 3.3v, 2.5v) (v ddq = 3.3v, 2.5v) (v dd = 1.5v) (v dd = 1.5v) (v dd = 1.65v) min. max. min. max. min. max. 1f clock clk2x frequency. 40 133 40 166 40 200 mhz 2t clok pll lock time. 0.5 0.5 0.5 ms 3t ckhi clk2x high pulse. [17] 3.0 2.4 2.0 ns 4t cklo clk2x low pulse. [17] 3.0 2.4 2.0 ns 5t isch input set-up time to clk2x rising edge. [17] 2.5 1.8 1.5 ns 6t ihch input hold time to clk2x rising edge. [17] commercial 0.6 0.6 0.5 ns industrial 0.8 0.8 ns 7t icsch cascaded input set-up time to clk2x rising edge. [17] 4.2 3.5 3.0 ns 8t ichch cascaded input hold time to clk2x rising edge. [17] 2.0 2.0 2.0 ns 9t ckhov rising edge of clk2x to lho, fulo, bho, full valid. [18] 8.5 7.0 6.5 ns 10 t ckhdv rising edge of clk2x to dq valid. [18] 9.0 7.5 7.0 ns 11 t ckhdz rising edge of clk2x to dq high-z. [19] 0.5 8.5 0.5 7.0 0.5 6.5 ns 12 t ckhsv rising edge of clk2x to sram bus valid. [18] 9.0 7.5 7.0 ns 13 t ckhshz rising edge of clk2x to sram bus high-z. [19] 0.5 6.5 0.5 6.0 0.5 5.5 ns 14 t ckhslz rising edge of clk2x to sram bus low-z. [19] 7.0 6.5 6.0 ns notes: 15. maximum allowable applies to overshoot only (v ddq is 2.5 v supply). 16. minimum allowable applies to undershoot only. 17. values are based on 50% signal levels. 18. based on an ac load of cl = 30 pf (see figure 17-1 , figure 17-2 , and figure 17-3 ). 19. these parameters are sampled but not 100% tested, and are based on an ac load of 5 pf.
cynse7012 8 document #: 38-02040 rev. *e page 126 of 137 table 17-2. ac timing parameters with clk1x row parameter description cynse70128 -066 cynse70128 -083 cynse70128 -100 unit (v ddq = 3.3v, 2.5v) (v ddq = 3.3v, 2.5v) (v ddq = 3.3v, 2.5v) (v dd = 1.5v) (v dd = 1.5v) (v dd = 1.65v) min. max. min. max. min. max. 1f clock clk1x frequency. 2066208320100mhz 2t clok pll lock time. 0.5 0.5 0.5 ms 3t ckhi clk1x high pulse. [20] 6.75 5.4 4.5 ns 4t cklo clk1x low pulse. [20] 6.75 5.4 4.5 ns 5t isch input set-up time to clk1x edge. [20] 2.5 1.8 1.5 ns 6t ihch input hold time to clk1x edge. [20] commercial 0.6 0.6 0.5 ns industrial 0.9 0.9 ns 7t icsch cascaded input set-up time to clk1x rising edge. [20] 4.2 3.5 3.0 ns 8t ichch cascaded input hold time to clk1x rising edge. [20] 2.0 2.0 2.0 ns 9t ckhov rising edge of clk1x to lho, fulo, bho, full valid. [21] 8.5 7.0 6.5 ns 10 t ckhdv rising edge of clk1x to dq valid. [21] 9.0 7.5 7.0 ns 11 t ckhdz rising edge of clk1x to dq high-z. [22] 0.5 8.5 0.5 7.0 0.5 6.5 ns 12 t ckhsv rising edge of clk1x to sram bus valid. [21] 9.0 7.5 7.0 ns 13 t ckhshz rising edge of clk1x to sram bus high-z. [22] 0.5 6.5 0.5 6.0 0.5 5.5 ns 14 t ckhslz rising edge of clk1x to sram bus low-z. [22] 7.0 6.5 6.0 ns table 17-3. 2.5v ac table for test condition of cynse70128 conditions results input pulse levels (v ddq = 3.3v) gnd to 3.0v input pulse levels (v ddq = 2.5v) gnd to 2.5v input rise and fall times measured at 0.3v and 2.7v (v ddq = 3.3v) 2 ns see figure 17-1 input rise and fall times measured at 0.25v and 2.25v (v ddq = 2.5v) 2 ns see figure 17-1 input timing reference levels (v ddq = 3.3v) 1.5v input timing reference levels (v ddq = 2.5v) 1.25 output reference levels (v ddq = 3.3v) 1.5v output reference levels (v ddq = 2.5v) 1.25v output load see figure 17-2 and figure 17-3 notes: 20. values are based on 50% signal levels and a 50%/50% duty cycle of clk1x. 21. based on an ac load of cl = 30 pf (see figure 17-1 , figure 17-2 , and figure 17-3 ). 22. these parameters are sampled but not 100% tested, and are based on an ac load of 5 pf.
cynse7012 8 document #: 38-02040 rev. *e page 127 of 137 figure 17-4 shows timing waveform diagrams for clk2x. figure 17-5 details timing waveform diagrams for clk1x. notes: 23. output loading is specified with c l = 5 pf, as in figure 17-3 . transition is measured at 200 mv from steady-state voltage. 24. the load used for voh, vol testing is shown in figure 17-3 . +2.5v v ddq = 2.5v / +3.0v v ddq = 3.3v 90% 90% 10% 10% gnd figure 17-1. input wave form for cynse70128 v l = 1.25v for v ddq = 2.5v v l = 1.5v for v ddq = 3.3v d out c l ac load z0 = 50 ? 50 ? figure 17-2. output load for cynse70128 5 pf 208 ? v ddq = 2.5v 158 ? v ddq = 3.3v 192 ? vddq = 2.5v 175 ? vddq = 3.3v q v ddq for high-z and v ol /v oh [23, 24] figure 17-3. i/o output load equivalent for cynse70128
cynse7012 8 document #: 38-02040 rev. *e page 128 of 137 clk signal signal signal signal signal group 0 group 2 group 3 group 5 group 4 0 t ihch t isch t icsch t ihch signal group 0: phs_l, rst_l. signal group 1: dq, cmd, cmdv. signal group 2: lhi, bhi, fuli. signal group 3: lho, bho, fulo, full. signal group 4: sadr, ce_l, oe_l, we_l, ale_l, ssf, ssv. signal group 5: dq, ack, eot. t ckhov t ckhov t ckhdz t ckhdv t ckhshz t ckhslz t ckhsv cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 cycle 11 cycle 12 cycle clk2x signal group 1 t ihch t isch t ihch t isch t ichch figure 17-4. ac timing waveforms with clk2x
cynse7012 8 document #: 38-02040 rev. *e page 129 of 137 17.1 special note for multi_hit function on the cynse70128 general description : the cynse70128 device provides a ?multi_hit? signal as an output. the purpose of this signal is to indicate the occurrence of a multiple hit on a search in the search engine. correct usage : in order to ensure correct function for multi_hit on cynse70128: backward compatibility mode (with cynse70032 and cynse70064): data array bits need to be used as table id bits. non-backward compatibility mode: either data array bits need to still be used as table id bits, or the entire data array needs to be configured with one table size. in multiple nse configuration (cascaded mode), the ?or? function for the multi_hits from each nse must be provided externally. the multi_hit signal should be sampled on four clk1x cycles (or on eight clk2x cycles) after the issue of the search command, regardless of the tlsz and hlat parameters in the command register. clk signal signal signal signal signal group 0 group 2 group 3 group 5 group 4 0 t ihch t isch t icsch t ihch signal group 0: phs_l, rst_l. signal group 1: dq, cmd, cmdv. signal group 2: lhi, bhi, fuli. signal group 3: lho, bho, fulo, full. signal group 4: sadr, ce_l, oe_l, we_l, ale_l, ssf, ssv. signal group 5: dq, ack, eot. t ckhov t ckhov t ckhdz t ckhdv t ckhshz t ckhslz t ckhsv cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 cycle 11 cycle 12 cycle clk1x signal group 1 t isch t ihch t sch t ichch figure 17-5. ac timing waveforms with clk1x
cynse7012 8 document #: 38-02040 rev. *e page 130 of 137 18.0 pinout description in the following figure and table, the cynse70128 device pinout diagram and descriptions are shown (see figure 18-1 and table 18-1 ). figure 18-1. pinout diagram af ae ad ac ab aa y w v u t r p n m l k j h g f e d c b a 1 nc v ss rst_l v ss full fulo1 fuli6 v ddq fuli2 fuli0 bho2 v ddq bho0 bhi1 v ddq lho0 lhi6 lhi2 lhi0 id3 id1 id0 trst _l tck tdi v dd 1 2 v ss v ss v ddq eot ack v ddq fulo0 fuli5 fuli3 v ddq v ss bho1 multi_hit bhi2 bhi0 lho1 lhi4 lhi3 lhi1 id4 id2 v ddq tdo tms v ss dq71 2 3 dq68 dq70 v dd v dd v dd v dd v dd nc fuli4 fuli1 v dd v dd v dd v dd v dd v dd lhi5 v ddq nc v dd v dd v dd v dd v dd dq69 v ddq 3 4 dq66 v ddq v dd v ss v ss v ss v ss v ss v ss v ss v dd v dd v dd v dd v dd v dd v ss v ss v ss v ss v ss v ss v ss v dd dq65 dq67 4 5 dq62 dq64 v dd v ss v ss v dd dq61 dq63 5 6 v ddq dq60 v dd v ss v ss v dd dq59 v ddq 6 7 dq56 dq58 v dd v ss v ss v dd dq55 dq57 7 8 dq52 dq54 nc v ss v ss nc v ddq dq53 8 9 dq48 dq50 v ddq v ss v ss dq49 dq47 dq51 9 10 v ddq dq44 dq46 v ss v ss v ddq dq45 dq43 10 11 dq40 dq42 v dd v dd v ss v ss v ss v ss v ss v ss v dd v dd dq39 dq41 11 12 dq36 dq38 v dd v dd v ss v ss v ss v ss v ss v ss v dd v dd v ddq dq37 12 13 dq34 v ddq v dd v dd v ss v ss v ss v ss v ss v ss v dd v dd dq33 dq35 13 14 dq30 dq32 v dd v dd v ss v ss v ss v ss v ss v ss v dd v dd dq29 dq31 14 15 v ddq dq28 v dd v dd v ss v ss v ss v ss v ss v ss v dd v dd dq27 v ddq 15 16 dq24 dq26 v dd v dd v ss v ss v ss v ss v ss v ss v dd v dd dq23 dq25 16 17 dq22 v ddq dq20 v ss v ss dq19 v ddq dq21 17 18 dq14 dq18 dq16 v ss v ss dq13 dq15 dq17 18 19 v ddq dq12 nc v ss v ss nc dq11 v ddq 19 20 dq08 dq10 v dd v ss v ss v dd dq07 dq09 20 21 dq04 dq06 v dd v ss v ss v dd v ddq dq05 21 22 dq02 v ddq v dd v ss v ss v dd dq01 dq03 22 23 ssv dq00 v dd v ss v ss v ss v ss v ss v ss v ss v dd v dd v dd v dd v dd v dd v ss v ss v ss v ss v ss v ss v ss v dd v ss v ss 23 24 ssf v ddq v dd v dd v dd v dd v dd nc ce_l oe_l v dd v dd v dd v dd v dd v dd sadr13 sadr11 nc v dd v dd v dd v dd v dd cfg_l v ddq 24 25 cmd10 v ss cmd8 cmd6 cmd5 cmd3 cmd1 cmdv v ddq phs_l clk_mode sadr22 sadr21 sadr19 v ddq sadr15 v ddq sadr12 v ddq sadr08 sadr06 sadr05 sadr 03 sadr0 1 v ss high_spee d 25 26 cmd9 v ss cmd7 v ddq cmd4 cmd2 cmd0 ale_l we_l clk1x/ clk2x sadr23 v ddq sadr20 sadr18 sadr17 sadr16 sadr14 sadr10 sadr0 9 sadr07 v ddq sadr04 sadr 02 v ddq sadr0 0 v dd 26 af ae ad ac ab aa y w v u t r p n m l k j h g f e d c b a
cynse7012 8 document #: 38-02040 rev. *e page 131 of 137 table 18-1. pinout descriptions for pinout diagram package ball number signal name signal type package ball number signal name signal type a1 v ddq 2.5v/3.3v aa26 cmd[2] input a10 dq[43] i/o aa3 v dd 1.5v/1.65v a11 dq[41] i/o aa4 v ss ground a12 dq[37] i/o ab1 full output-t a13 dq[35] i/o ab2 ack output-t a14 dq[31] i/o ab23 vss ground a15 v ddq [25] 2.5v/3.3v ab24 v dd 1.5v/1.65v a16 dq[25] i/o ab25 cmd[5] input a17 dq[21] i/o ab26 cmd[4] input a18 dq[17] i/o ab3 v dd 1.5v/1.65v a19 v ddq 2.5v/3.3v ab4 v ss ground a2 dq[71] i/o ac1 v ss ground a20 dq[09] i/o ac10 v ss ground a21 dq[05] i/o ac11 v dd 1.5v/1.65v a22 dq[03] i/o ac12 v dd 1.5v/1.65v a23 v ss ground ac13 v dd 1.5v/1.65v a24 v ddq 2.5v/3.3v ac14 v dd 1.5v/1.65v a25 high_speed input ac15 v dd 1.5v/1.65v a26 v ddq 2.5v/3.3v ac16 v dd 1.5v/1.65v a3 v ddq 2.5v/3.3v ac17 v ss ground a4 dq[67] i/o ac18 v ss ground a5 dq[63] i/o ac19 v ss ground a6 v ddq 2.5v/3.3v ac2 eot output-t a7 dq[57] i/o ac20 v ss ground a8 dq[53] i/o ac21 v ss ground a9 dq[51] i/o ac22 v ss ground aa1 fulo[1] output-t ac23 v ss ground aa2 v ddq 2.5v/3.3v ac24 v dd 1.5v/1.65v aa23 v ss ground ac25 cmd[6] input aa24 v dd 1.5v/1.65v ac26 v ddq 2.5v/3.3v aa25 cmd[3] input ac3 v dd 1.5v/1.65v ac4 v ss ground ae10 dq[44] i/o ac5 v ss ground ae11 dq[42] i/o ac6 v ss ground ae12 dq[38] i/o ac7 v ss ground ae13 v ddq 2.5v/3.3v ac8 v ss ground ae14 dq[32] i/o ac9 v ss ground ae15 dq[28] i/o ad1 rst_l input ae16 dq[26] i/o ad10 dq[46] i/o ae17 v ddq 2.5v/3.3v ad11 v dd 1.5v/1.65v ae18 dq[18] i/o ad12 v dd 1.5v/1.65v ae19 dq[12] i/o ad13 v dd 1.5v/1.65v ae2 v ss ground ad14 v dd 1.5v/1.65v ae20 dq[10] i/o
cynse7012 8 document #: 38-02040 rev. *e page 132 of 137 ad15 v dd 1.5v/1.65v ae21 dq[06] i/o ad16 v dd 1.5v/1.65v ae22 v ddq 2.5v/3.3v ad17 dq[20] i/o ae23 dq[00] i/o ad18 dq[16] i/o ae24 v ddq 2.5v/3.3v ad19 nc no connect ae25 v ss ground ad2 v ddq 2.5v/3.3v ae26 v ss ground ad20 v dd 1.5v/1.65v ae3 dq[70] i/o ad21 v dd 1.5v/1.65v ae4 v ddq 2.5v/3.3v ad22 v dd 1.5v/1.65v ae5 dq[64] i/o ad23 v dd 1.5v/1.65v ae6 dq[60] i/o ad24 v dd 1.5v/1.65v ae7 dq[58] i/o ad25 cmd[8] input ae8 dq[54] i/o ad26 cmd[7] input ae9 dq[50] i/o ad3 v dd 1.5v/1.65v af1 nc no connect ad4 v dd 1.5v/1.65v af10 v ddq 2.5v/3.3v ad5 v dd 1.5v/1.65v af11 dq[40] i/o ad6 v dd 1.5v/1.65v af12 dq[36] i/o ad7 v dd 1.5v/1.65v af13 dq[34] i/o ad8 nc no connect af14 dq[30] i/o ad9 v ddq 2.5v/3.3v af15 v ddq 2.5v/3.3v ae1 v ss ground af16 dq[24] i/o af17 dq[22] i/o b23 v ss ground af18 dq[14] i/o b24 cfg_l input af19 v ddq 2.5v/3.3v b25 v ss ground af2 v ss ground b26 sadr[00] output af20 dq[08] i/o b3 dq[69] i/o af21 dq[04] i/o b4 dq[65] i/o af22 dq[02] i/o b5 dq[61] i/o af23 ssv output-t b6 dq[59] i/o af24 ssf output-t b7 dq[55] i/o af25 cmd[10] input b8 v ddq 2.5v/3.3v af26 cmd[9] input b9 dq[47] i/o af3 dq[68] i/o c1 tck input af4 dq[66] i/o c10 v ddq 2.5v/3.3v af5 dq[62] i/o c11 v dd 1.5v/1.65v af6 v ddq 2.5v/3.3v c12 v dd 1.5v/1.65v af7 dq[56] i/o c13 v dd 1.5v/1.65v af8 dq[52] i/o c14 v dd 1.5v/1.65v af9 dq[48] i/o c15 v dd 1.5v/1.65v b1 tdi input c16 v dd 1.5v/1.65v b10 dq[45] i/o c17 dq[19] i/o b11 dq[39] i/o c18 dq[13] i/o b12 v ddq 2.5v/3.3v c19 nc no connect table 18-1. pinout descriptions for pinout diagram (continued) package ball number signal name signal type package ball number signal name signal type
cynse7012 8 document #: 38-02040 rev. *e page 133 of 137 b13 dq[33] i/o c2 tms input b14 dq[29] i/o c20 v dd 1.5v/1.65v b15 dq[27] i/o c21 v dd 1.5v/1.65v b16 dq[23] i/o c22 v dd 1.5v/1.65v b17 v ddq 2.5v/3.3v c23 v dd 1.5v/1.65v b18 dq[15] i/o c24 v dd 1.5v/1.65v b19 dq[11] i/o c25 sadr[01] output b2 v ss ground c26 v ddq 2.5v/3.3v b20 dq[07] i/o c3 v dd 1.5v/1.65v b21 v ddq 2.5v/3.3v c4 v dd 1.5v/1.65v b22 dq[01] i/o c5 v dd 1.5v/1.65v c6 v dd 1.5v/1.65v e24 v dd 1.5v/1.65v c7 v dd 1.5v/1.65v e25 sadr[05] output c8 nc no connect e26 sadr[04] output c9 dq[49] i/o e3 v dd 1.5v/1.65v d1 trst_l input e4 v ss ground d10 vss ground f1 id[1] input d11 v dd 1.5v/1.65v f2 id[2] input d12 v dd 1.5v/1.65v f23 v ss ground d13 v dd 1.5v/1.65v f24 v dd 1.5v/1.65v d14 v dd 1.5v/1.65v f25 sadr[06] output d15 v dd 1.5v/1.65v f26 v ddq 2.5v/3.3v d16 v dd 1.5v/1.65v f3 v dd 1.5v/1.65v d17 v ss ground f4 v ss ground d18 v ss ground g1 id[3] input d19 v ss ground g2 id[4] input d2 tdo output-t g23 v ss ground d20 v ss ground g24 v dd 1.5v/1.65v d21 v ss ground g25 sadr[08] output d22 v ss ground g26 sadr[07] output d23 v ss ground g3 v dd 1.5v/1.65v d24 v dd 1.5v/1.65v g4 v ss ground d25 sadr[03] output h1 lhi[0] input d26 sadr[02] output h2 lhi[1] input d3 v dd 1.5v/1.65v h23 v ss ground d4 v ss ground h24 nc no connect d5 v ss ground h25 v ddq 2.5v/3.3v d6 v ss ground h26 sadr[09] output d7 v ss ground h3 nc no connect d8 v ss ground h4 v ss ground d9 v ss ground j1 lhi[2] input e1 id[0] input j2 lhi[3] input e2 v ddq 2.5v/3.3v j23 v ss ground table 18-1. pinout descriptions for pinout diagram (continued) package ball number signal name signal type package ball number signal name signal type
cynse7012 8 document #: 38-02040 rev. *e page 134 of 137 e23 v ss ground j24 sadr[11] output j25 sadr[12] output m2 bhi[0] input j26 sadr[10] output m23 v dd 1.5v/1.65v j3 v ddq 2.5v/3.3v m24 v dd 1.5v/1.65v j4 v ss ground m25 v ddq 2.5v/3.3v k1 lhi[6] input m26 sadr[17] output k2 lhi[4] input m3 v dd 1.5v/1.65v k23 v ss ground m4 v dd 1.5v/1.65v k24 sadr[13] output n1 bhi[1] input k25 v ddq 2.5v/3.3v n11 v ss ground k26 sadr[14] output n12 v ss ground k3 lhi[5] input n13 v ss ground k4 v ss ground n14 v ss ground l1 lho[0] output-t n15 v ss ground l11 v ss ground n16 v ss ground l12 v ss ground n2 bhi[2] input l13 v ss ground n23 v dd 1.5v/1.65v l14 v ss ground n24 v dd 1.5v/1.65v l15 v ss ground n25 sadr[19] output l16 v ss ground n26 sadr[18] output l2 lho[1] output-t n3 v dd 1.5v/1.65v l23 v dd 1.5v/1.65v n4 v dd 1.5v/1.65v l24 v dd 1.5v/1.65v p1 bho[0] output-t l25 sadr[15] output p11 v ss ground l26 sadr[16] output p12 v ss ground l3 v dd 1.5v/1.65v p13 v ss ground l4 v dd 1.5v/1.65v p14 v ss ground m1 v ddq 2.5v/3.3v p15 v ss ground m11 v ss ground p16 v ss ground m12 v ss ground p2 multi_hit output-t m13 v ss ground p23 v dd 1.5v/1.65v m14 v ss ground p24 v dd 1.5v/1.65v m15 v ss ground p25 sadr[21] output m16 v ss ground p26 sadr[20] output p3 v dd 1.5v/1.65v u24 oe_l output-t p4 v dd 1.5v/1.65v u25 phs_l input r1 v ddq 2.5v/3.3v u26 clk1x/clk2x input r11 v ss ground u3 fuli[1] input r12 v ss ground u4 v ss ground r13 v ss ground v1 fuli[2] input r14 v ss ground v2 fuli[3] input r15 v ss ground v23 v ss ground r16 v ss ground v24 ce_l output-t table 18-1. pinout descriptions for pinout diagram (continued) package ball number signal name signal type package ball number signal name signal type
cynse7012 8 document #: 38-02040 rev. *e page 135 of 137 19.0 ordering information table 19-1 provides ordering information. r2 bho[1] output-t v25 v ddq 2.5v/3.3v r23 v dd 1.5v/1.65v v26 we_l output-t r24 v dd 1.5v/1.65v v3 fuli[4] input r25 sadr[22] output v4 v ss ground r26 v ddq 2.5v/3.3v w1 v ddq 2.5v/3.3v r3 v dd 1.5v/1.65v w2 fuli[5] input r4 v dd 1.5v/1.65v w23 v ss ground t1 bho[2] output-t w24 nc no connect t11 v ss ground w25 cmdv input t12 v ss ground w26 ale_l output-t t13 v ss ground w3 nc no connect t14 v ss ground w4 v ss ground t15 v ss ground y1 fuli[6] input t16 v ss ground y2 fulo[0] output-t t2 v ss ground y23 v ss ground t23 v dd 1.5v/1.65v y24 v dd 1.5v/1.65v t24 v dd 1.5v/1.65v y25 cmd[1] input t25 clk_mode input y26 cmd[0] input t26 sadr[23] output y3 v dd 1.5v/1.65v t3 v dd 1.5v/1.65v y4 v ss ground t4 v dd 1.5v/1.65v u1 fuli[0] input u2 v ddq 2.5v/3.3v u23 v ss ground table 19-1. ordering information part number description i/o voltage frequency temperature range cynse70128?66bgc nse 2.5v/3.3v 66 mhz commercial cynse70128?66bgi nse 2.5v/3.3v 66 mhz industrial cynse70128?83bgc nse 2.5v/3.3v 83 mhz commercial cynse70128?83bgi nse 2.5v/3.3v 83 mhz industrial cynse70128?100bgc nse 2.5v/3.3v 100 mhz commercial note: 25. all v ddq pins should be set to 2.5v or 3.3v (cynse70128). table 18-1. pinout descriptions for pinout diagram (continued) package ball number signal name signal type package ball number signal name signal type
cynse7012 8 document #: 38-02040 rev. *e page 136 of 137 ? cypress semiconductor corporation, 2003. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semi conductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support syst ems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies th at the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. 20.0 package diagram apt is a trademark of cypress semiconductor. all product and company names mentioned in this document are the trademarks of their respective holders. figure 20-1. 388-lead ball grid array (35 x 35 x 2.33 mm) bg388 51-85103-*c
cynse7012 8 document #: 38-02040 rev. *e page 137 of 137 document history page document title: cynse70128 network search engine document number: 38-02040 rev. ecn no. issue date orig. of change description of change ** 111436 01/29/02 afx new data sheet *a 116609 08/28/02 oor updated ac timing, dc char, jtag, pinout diagram and pinout description. removed references to test signals from pinout diagram, pinout description and signal description. added power section covering power-up sequence and power consumption. removed all references to 1.8v i/o. removed all references to clk_tune[3:0] and set it to 100% (?1001?). *b 119295 12/16/02 ed added availability of 66- and 83-mhz industrial parts. removed clk1x power-up sequence diagrams. added note to power-up sequence instructions. added operating temperature range of industrial parts. added minimum output data hold (t ckhdz and t ckhshz ) of 0.5 ns. changed cascaded input hold time (t ichch ) to 2.0 ns. corrected pinout signal name for ae26, af2: v dd to v ss . added industrial parts ordering information. removed alternative power-up sequence instructions: toc, figure 13-3 . *c 123794 02/20/03 kos added 3.3v to the i/o voltage of cynse70128-83bgi ordering information. corrected section 10.6.10 figure number reference from figure 12-37 to figure 10-71 . corrected section 10.6.10 figure number reference from figure 12-38 to figure 10-72 . changed cascaded input hold time (t ichch ) to 2.0ns. changed input hold time to clk1x edge (t ihch ) for cynse70128-66 to 0.6 ns. changed input hold time to clk1x edge (t ihch ) for cynse70128-83 to 0.6 ns. changed input hold time to clk1x edge (t ihch ) for cynse70128-100 to 0.5 ns. added input hold time to clk2x edge (t ihch ) ac characteristic for industrial parts. added input hold time to clk1x edge (t ihch ) ac characteristic for industrial parts. *d 126021 05/08/03 itl updated figure 13-1 on page 121 to reflect the correct waveforms. also corrected the power-up sequence above the figure. corrected the pin description of ae26 in the pin assignment table. the description is changed to ?ground.? *e 127445 06/25/03 dcu clarified description of high_speed pin. amended learn description to include restriction at >83 mhz.

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